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july 2003 the following document specifies spansion memory products that are now offered by both advanced micro devices and fujitsu. although the document is marked with the name of the company that orig- inally developed the specification, these products will be offered to customers of both amd and fujitsu. continuity of specifications there is no change to this datasheet as a result of offering the device as a spansion product. any changes that have been made are the result of normal datasheet improvement and are noted in the document revision summary, where supported. future routine revisions will occur when appropriate, and changes will be noted in a revision summary. continuity of ordering part numbers amd and fujitsu continue to support existing part numbers beginning with ?am? and ?mbm?. to order these products, please use only the ordering part numbers listed in this document. for more information please contact your local amd or fujitsu sales office for additional information about spansion memory solutions. am29lv640mh/l data sheet publication number 26191 revision f amendment 0 issue date august 14, 2003
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publication number 26191 revision f amendment 0 issue date august 14, 2003 advance information am29lv640mh/l 64 megabit (4 m x 16-bit/8 m x 8-bit) mirrorbit ? 3.0 volt-only uniform sector flash memory with versatilei/o ? control data sheet distinctive characteristics architectural advantages ? single power supply operation ? 3 v for read, erase, and program operations ? versatilei/o ? control ? device generates data output voltages and tolerates data input voltages on the dq inputs/outputs as determined by the voltage on the v io pin; operates from 1.65 to 3.6 v ? manufactured on 0.23 m mirrorbit process technology ? secsi ? (secured silicon) sector region ? 128-word/256-byte sector for permanent, secure identification through an 8-word/16-byte random electronic serial number, accessible through a command sequence ? may be programmed and locked at the factory or by the customer ? flexible sector architecture ? one hundred twenty-eight 32 kword/64-kbyte sectors ? compatibility with jedec standards ? provides pinout and software compatibility for single- power supply flash, and superior inadvertent write protection ? minimum 100,000 erase cycle guarantee per sector ? 20-year data retention at 125 c performance characteristics ? high performance ? 90 ns access time ? 25 ns page read times ? 0.5 s typical sector erase time ? 22 s typical effective write buffer word programming time: 16-word/32-byte write buffer reduces overall programming time for multiple-word/ byte updates ? 4-word/8-byte page read buffer ? 16-word/32-byte write buffer ? low power consumption (typical values at 3.0 v, 5 mhz) ? 30 ma typical active read current ? 50 ma typical erase/program current ? 1 a typical standby mode current ? package options ?56-pin tsop ? 64-ball fortified bga software features ? program suspend & resume: read other sectors before programming operation is completed ? erase suspend & resume: read/program other sectors before an erase operation is completed ? data# polling & toggle bits provide status ? unlock bypass program command reduces overall multiple-word programming time ? cfi (common flash interface) compliant: allows host system to identify and accommodate multiple flash devices hardware features ? sector group protection: hardware-level method of preventing write operations within a sector group ? temporary sector unprotect: v id -level method of changing code in locked sectors ? wp#/acc input: write protect input (wp#) protects first or last sector regardless of sector protection settings acc (high voltage) accelerates programming time for higher throughput during system production ? hardware reset input (reset#) resets device ? ready/busy# output (ry/by#) indicates program or erase cycle completion
2am29lv640mh/l 26191f0 august 14, 2003 advance information general description the am29lv640mh/l is a 64 mbit, 3.0 volt single power supply flash memory de- vice organized as 4,194,304 words or 8,388,608 bytes. the device has an 8-bit/ 16-bit bus and can be programmed either in the host system or in standard eprom programmers. an access time of 90, 100, 110, or 120 ns is available. note that each access time has a specific operating voltage range (v cc ) and an i/o voltage range (v io ), as specified in the product selector guide and the ordering information sections. the device is offered in a 56-pin tsop or 64-ball fortified bga package. each de- vice has separate chip enable (ce#), write enable (we#) and output enable (oe#) controls. each device requires only a single 3.0 volt power supply for both read and write functions. in addition to a v cc input, a high-voltage accelerated program (acc) feature provides shorter programming times through increased current on the wp#/acc input. this feature is intended to facilitate factory throughput dur- ing system production, but may also be used in the field if desired. the device is entirely command set compatible with the jedec single-power- supply flash standard . commands are written to the device using standard mi- croprocessor write timing. write cycles also internally latch addresses and data needed for the programming and erase operations. the sector erase architecture allows memory sectors to be erased and repro- grammed without affecting the data contents of other sectors. the device is fully erased when shipped from the factory. device programming and erasure are initiated through command sequences. once a program or erase operation has beg un, the host system need only poll the dq7 (data# polling) or dq6 (toggle) status bits or monitor the ready/busy# (ry/by#) output to determine whether the op eration is complete. to facilitate programming, an unlock bypass mode reduces command sequence overhead by requiring only two write cycles to program data instead of four. the versatilei/o? (v io ) control allows the host syst em to set the voltage levels that the device generates and tolerates on the ce# control input and dq i/os to the same voltage level that is asserted on the v io pin. refer to the ordering in- formation section for valid v io options. hardware data protection measures include a low v cc detector that automat- ically inhibits write operations during power transitions. the hardware sector protection feature disables both program and erase operations in any combina- tion of sectors of memory. this can be achieved in-system or via programming equipment. the erase suspend/erase resume feature allows the host system to pause an erase operation in a given sector to read or program any other sector and then complete the erase operation. the program suspend/program resume fea- ture enables the host system to pause a program operation in a given sector to read any other sector and then complete the program operation. the hardware reset# pin terminates any operation in progress and resets the device, after which it is then ready for a new operation. the reset# pin may be tied to the system reset circuitry. a system reset would thus also reset the device, enabling the host system to read b oot-up firmware from the flash memory device.
august 14, 2003 26191f0 am29lv640mh/l 3 advance information the device reduces power consumption in the standby mode when it detects specific voltage levels on ce# and reset#, or when addresses have been stable for a specified period of time. the write protect (wp#) feature protects the first or last sector by asserting a logic low on the wp#/acc pin. the protected sector will still be protected even during accelerated programming. the secsi ? (secured silicon) sector provides a 128-word/256-byte area for code or data that can be permanently pr otected. once this sector is protected, no further changes within the sector can occur. spansion mirrorbit flash technology comb ines years of flash memory manufac- turing experience to produce the highest levels of quality, reliability and cost effectiveness. the device electrically erases all bits within a sector simultaneously via hot-hole assisted erase. the data is programmed using hot electron injection.
4am29lv640mh/l 26191f0 august 14, 2003 advance information mirrorbit 64 mbit device family related documents to download related documents, clic k on the following links or go to www.amd.com flash memory product information mirrorbit flash infor- mation technical documentation. mirrorbit? flash memory write buffer programming and page buffer read implementing a common layout for amd mirrorbit and intel strataflash memory devices migrating from single-byte to three-byte device ids amd mirrorbit? white paper device bus sector architecture packages v io ry/ by# wp#, acc wp# protection lv065mu x8 uniform (64 kbyte) 48-pin tsop (std. & rev. pinout), 63-ball fbga yes yes acc only no wp# lv640mt/ b x8/ x16 boot (8 x 8 kbyte at top & bottom) 48-pin tsop, 63-ball fine-pitch bga, 64-ball fortified bga no yes wp#/acc pin 2 x 8 kbyte top or bottom lv640mh/ l x8/ x16 uniform (64 kbyte) 56-pin tsop (std. & rev. pinout), 64-ball fortified bga yes yes wp#/acc pin 1 x 64 kbyte high or low lv641mh/ l x16 uniform (32 kword) 48-pin tsop (std. & rev. pinout) yes no separate wp# and acc pins 1 x 32 kword top or bottom lv640mu x16 uniform (32 kword) 64-ball fortified bga, 64-ball fine-pitch bga yes yes acc only no wp#
august 14, 2003 26191f0 am29lv640mh/l 5 preliminary table of contents product selector guide . . . . . . . . . . . . . . . . . . . . . .6 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 connection diagrams . . . . . . . . . . . . . . . . . . . . . . .7 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 logic symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 ordering information . . . . . . . . . . . . . . . . . . . . . . . 10 device bus operations . . . . . . . . . . . . . . . . . . . . . . 11 table 1. device bus operations ...........................................11 word/byte configuration ....................................................................12 versatileio ? (v io ) control ............................................................... 12 requirements for reading array data ........................................... 12 writing commands/command sequences ................................... 13 standby mode ..........................................................................................14 automatic sleep mode ......................................................................... 14 reset#: hardware reset pin ............................................................ 14 output disable mode ........................................................................... 14 autoselect mode ....................................................................................19 table 2. autoselect codes, (high voltage method) ................19 sector group protection and unprotection ................................ 19 table 3. sector group protection/unprotection address table 20 write protect (wp#) ............................................................................21 temporary sector group unprotect ............................................. 21 figure 1. temporary sector group unprotect operation ......... 21 figure 2. in-system sector group protect/unprotect algorithms ............................................. 22 secsi (secured silicon) sector flash memory region ............... 23 figure 3. secsi sector protect verify ................................... 24 hardware data protection ................................................................ 24 common flash memory interface (cfi) . . . . . . . 25 table 4. cfi query identification string .................................... 26 system interface string..................................................... 26 table 6. device geometry definition......................................... 27 table 7. primary vendor-specific extended query................ 28 command definitions . . . . . . . . . . . . . . . . . . . . . . 28 reading array data ............................................................................. 29 reset command ................................................................................... 29 autoselect command sequence ...................................................... 30 enter secsi sector/exit secsi sector command sequence ..... 30 word/byte program command sequence ................................... 30 figure 4. write buffer programming operation...................... 33 figure 5. program operation .............................................. 34 program suspend/program resume command sequence ...... 34 figure 6. program suspend/program resume ....................... 35 chip erase command sequence .......................................................35 sector erase command sequence .................................................. 36 figure 7. erase operation .................................................. 37 erase suspend/erase resume commands .....................................37 command definitions ..........................................................................39 command definitions (x16 mode, byte# = v ih ) ................... 39 command definitions (x8 mode, byte# = v il )...................... 40 write operation status . . . . . . . . . . . . . . . . . . . . . 41 dq7: data# polling ............................................................................... 41 figure 8. data# polling algorithm....................................... 42 ry/by#: ready/ busy# .......................................................................... 43 dq6: toggle bit i ..................................................................................43 figure 9. toggle bit algorithm............................................ 44 dq2: toggle bit ii ................................................................................ 44 reading toggle bits dq6/dq2 ........................................................45 dq5: exceeded timing limits ...........................................................45 dq3: sector erase timer ...................................................................45 dq1: write-to-buffer abort ............................................................. 46 table 10. write operation status ........................................ 46 absolute maximum ratings . . . . . . . . . . . . . . . . . 47 figure 10. maximum negative overshoot waveform ............. 47 figure 11. maximum positive overshoot waveform ........................................................ 47 operating ranges . . . . . . . . . . . . . . . . . . . . . . . . . 47 dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . 48 test conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 figure 12. test setup ....................................................... 49 table 11. test specifications .............................................. 49 key to switching waveforms . . . . . . . . . . . . . . . . 49 figure 13. input waveforms and measurement levels ......................................................... 49 ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . 50 read-only operations ...................................................................... 50 figure 14. read operation timings ..................................... 50 figure 15. page read timings ............................................ 51 hardware reset (reset#) .................................................................52 figure 16. reset timings ................................................... 52 erase and program operations ........................................................53 figure 17. program operation timings ................................ 54 figure 18. accelerated program timing diagram................... 54 figure 19. chip/sector erase operation timings ................... 55 figure 20. data# polling timings (during embedded algorithms) .......................................... 56 figure 21. toggle bit timings (during embedded algorithms). 57 figure 22. dq2 vs. dq6 .................................................... 57 temporary sector unprotect .......................................................... 58 figure 23. temporary sector group unprotect timing diagram 58 figure 24. sector group protect and unprotect timing diagram 59 alternate ce# controlled erase and program operations ... 60 figure 25. alternate ce# controlled write (erase/program) operation timings ............................................................ 61 erase and programming performance . . . . . . . . 62 latchup characteristics . . . . . . . . . . . . . . . . . . . . . 62 tsop pin and bga package capacitance. . . . . . 63 data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 physical dimensions . . . . . . . . . . . . . . . . . . . . . . . 64 ts056/tsr056?56-pin standard and reverse pinout thin small outline package (tsop) ............................................... 64 laa064?64-ball fortified ball grid array ( f bga) 13 x 11 mm package .....................................................................................................65 revision summary . . . . . . . . . . . . . . . . . . . . . . . . . 66
6am29lv640mh/l 26191f0 august 14, 2003 preliminary product selector guide notes: 1. see ?ac characteristics? for full specifications. 2. for the am29lv640mh-l device, the last numeric digit in the speed option (e.g. 101 , 112 , 120 ) is used for internal purposes only. please use opns as listed on p. 9 when placing orders. block diagram part number am29lv640mh/l speed option v cc = 3.0?3.6 v 90r (v io = 3.0? 3.6 v) 101r (v io = 2.7? 3.6 v) 112r (v io = 1.65? 3.6 v) 120r (v io = 1.65 ?3.6 v) v cc = 2.7?3.6 v 101 (v io = 2.7? 3.6 v) 112 (v io = 1.65 ?3.6 v) 120 (v io = 1.65? 3.6 v) max. access time (ns) 90 100 110 120 max. ce# access time (ns) 90 100 110 120 max. page access time (t pacc ) 25 30 30 40 30 40 max. oe# access time (ns) 25 30 30 40 30 40 input/output buffers x-decoder y-decoder chip enable output enable logic erase voltage generator pgm voltage generator timer v cc detector state control command register v cc v ss we# wp#/acc byte# ce# oe# stb stb dq0 ? dq15 (a-1) sector switches ry/by# reset# data latch y-gating cell matrix address latch a21?a0 v io
august 14, 2003 26191f0 am29lv640mh/l 7 advance information connection diagrams 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 nc nc 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 nc nc 23 24 25 26 27 28 nc nc 34 33 32 31 30 29 nc v io a15 a18 a14 a13 a12 a11 a10 a9 a8 a19 a20 we# reset# a21 wp#/acc ry/by# a1 a17 a7 a6 a5 a4 a3 a2 a16 dq2 byte# v ss dq15/a-1 dq7 dq14 dq6 dq13 dq9 dq1 dq8 dq0 oe# v ss ce# a0 dq5 dq12 dq4 v cc dq11 dq3 dq10 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 nc nc a15 a14 a13 a12 a11 a10 a9 a8 a19 a20 we# reset# a21 wp#/acc ry/by# a18 a17 a7 a6 a5 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 nc nc a16 byte# v ss dq15/a-1 dq7 dq14 dq6 dq13 dq5 dq12 dq4 v cc dq11 dq3 dq10 dq2 dq9 dq1 dq8 dq0 23 24 25 26 27 28 a4 a3 a2 a1 nc nc 34 33 32 31 30 29 oe# v ss ce# a0 nc v io 56-pin standard tsop 56-pin reverse tsop
8am29lv640mh/l 26191f0 august 14, 2003 advance information connection diagrams special package handling instructions special handling is required for flash memory products in molded packages (tsop and bga). the package and/or data integrity may be compromised if the package body is exposed to temperatures above 150 c for prolonged periods of time. b3 c3 d3 e3 f3 g3 h3 b4 c4 d4 e4 f4 g4 h4 b5 c5 d5 e5 f5 g5 h5 b6 c6 d6 e6 f6 g6 h6 b7 c7 d7 e7 f7 g7 h7 b8 c8 d8 e8 f8 g8 h8 nc nc nc v ss v io nc nc v ss dq15/a-1 byte# a16 a15 a14 a12 dq6 dq13 dq14 dq7 a11 a10 a8 dq4 v cc dq12 dq5 a19 a21 reset# dq3 dq11 dq10 dq2 a20 a18 wp#/acc dq1 dq9 dq8 dq0 a5 a6 a17 a3 a4 a5 a6 a7 a8 nc a13 a9 we# ry/by# a7 b2 c2 d2 e2 f2 g2 h2 v ss oe# ce# a0 a1 a2 a4 a2 a3 b1 c1 d1 e1 f1 g1 h1 nc nc v io nc nc nc nc a1 nc 64-ball fortified bga top view, balls facing down
august 14, 2003 26191f0 am29lv640mh/l 9 advance information pin description a21?a0 = 22 address inputs dq14?dq0 = 15 data inputs/outputs dq15/a-1 = dq15 (data input/output, word mode), a-1 (lsb address input, byte mode) ce# = chip enable input oe# = output enable input we# = write enable input wp#/acc = hardware write protect input/programming acceleration input reset# = hardware reset pin input ry/by# = ready/busy output byte# = selects 8-bit or 16-bit mode v cc = 3.0 volt-only single power supply (see product selector guide for speed options and voltage supply tolerances) v io = output buffer power v ss = device ground nc = pin not connected internally logic symbol 22 16 or 8 dq15?dq0 (a-1) a21?a0 ce# oe# we# reset# ry/by# wp#/acc v io byte#
10 am29lv640mh/l 26191f0 august 14, 2003 advance information ordering information standard products standard products are available in several packages and operating ranges. the order number (valid combination) is formed by a combination of the following: valid combinations valid combinations list configurations planned to be supported in volume for this device. consult the local amd sales office to confirm availability of specific valid combinations and to check on newly released combinations. notes: 1. for the am29lv640mh-l device, the last numeric digit in the speed option (e.g. 101 , 112 , 120 ) is used for internal purposes only. 2. to select product with esn factory-locked into the secsi sector: 1) select order number from the valid combinations given above, 2) add designator ?n? at the end of the order number, and 3) modify the speed option indicator as follows [101r = 10r, 112r = 11r, 120r = 12r, 90r, 101, 112, 120 = no change] example: am29lv640mh12rpcin. for fortified bga packages, the designator ?n? will also appear at the end of the package marking. example: l640mh12nin. am29lv640m h 120r pc i temperature range i = industrial (?40 c to +85 c) package type e = 56-pin thin small outline package (tsop) standard pinout (ts 056) f = 56-pin thin small outline package (tsop) reverse pinout (tsr056) pc = 64-ball fortified ball grid array, 1.0 mm pitch, 13 x 11 mm package (laa064) speed option see product selector guide and valid combinations sector architecture and wp# protection (wp# = v il ) h = uniform sector device, highest address sector protected l = uniform sector device, lowest address sector protected device number/description am29lv640mh/l 64 megabit (4 m x 16-bit/8 m x 8-bit) mirrorbit ? uniform sector flash memory with versatileio ? control, 3.0 volt-only read, program, and erase valid combinations for tsop package (note 2) speed (ns) v io range (v) v cc range (v) am29lv640mh90r am29lv640ml90r ei, fi 90 3.0?3.6 3.0?3.6 am29lv640mh112 am29lv640ml112 110 1.65?3.6 2.7?3.6 am29lv640mh120 am29lv640ml120 120 1.65?3.6 am29lv640mh101r am29lv640ml101r 100 2.7?3.6 3.0?3.6 am29lv640mh112r am29lv640ml112r 110 1.65?3.6 am29lv640mh120r am29lv640ml120r 120 1.65?3.6 valid combinations for fortified bga package (note 2) speed (ns) v io range (v) v cc range (v) order number package marking am29lv640mh90r am29lv640ml90r pci l640mh90ni l640ml90ni 90 3.0? 3.6 3.0? 3.6 am29lv640mh101 am29lv640ml101 l640mh01pi l640ml01pi 100 2.7? 3.6 2.7? 3.6 am29lv640mh112 am29lv640ml112 l640mh11pi l640ml11pi 110 1.65? 3.6 am29lv640mh120 am29lv640ml120 l640mh12pi l640ml12pi 120 1.65? 3.6 am29lv640mh101r am29lv640ml101r l640mh01ni l640ml01ni 100 2.7? 3. 3.0 ? 3.6 am29lv640mh112r am29lv640ml112r l640mh11ni l640ml11ni 110 1.65? 3.6 am29lv640mh120r am29lv640ml120r l640mh12ni l640ml12ni 120 1.65? 3.6
august 14, 2003 26191f0 am29lv640mh/l 11 advance information device bus operations this section describes the requirements and use of the device bus operations, which are initiated through the internal command register. the command register itself does not occupy any addressable memory location. the register is a latch used to store the commands, along with the address and data information needed to execute the command. the contents of the register serve as inputs to the internal state machine. the state machine outputs dictate the function of the device. tab l e 1 lists the device bus operations, the inputs and control levels they require, and the resulting output. the following subsections describe each of these operations in further detail. ta b l e 1 . device bus operations legend: l = logic low = v il , h = logic high = v ih , v id = 11.5?12.5 v, v hh = 11.5?12.5 v, x = don?t care, sa = sector address, a in = address in, d in = data in, d out = data out notes: 1. addresses are a21:a0 in word mode; a21:a-1 in byte mode. sector addresses are a21:a15 in both modes. 2. the sector protect and sector unprotect functions may also be implemented via programming equipment. see the ?sector group protection and unprotection? section. 3. if wp# = v il , the first or last sector remains protected. if wp# = v ih , the first or last sector will be protected or unprotected as determined by the method described in ?s ector group protection and unprotection?. all sectors are unprotected when shipped from the factory (the secsi sector may be factory protected depending on version ordered.) 4. d in or d out as required by command sequence, data polling , or sector protect algorithm (see figure 2). operation ce# oe# we # reset# wp# acc addresses (note 2) dq0? dq7 dq8?dq15 byte# = v ih byte# = v il read l l h h x x a in d out d out dq8?dq14 = high-z, dq15 = a-1 write (program/erase) l h l h (note 3) x a in (note 4) (note 4) accelerated program l h l h (note 3) v hh a in (note 4) (note 4) standby v cc 0.3 v xx v cc 0.3 v x h x high-z high-z high-z output disable l h h h x x x high-z high-z high-z reset x x x l x x x high-z high-z high-z sector group protect (note 2) lhl v id hx sa, a6 =l, a3=l, a2=l, a1=h, a0=l (note 4) x x sector group unprotect (note 2) lhl v id hx sa, a6=h, a3=l, a2=l, a1=h, a0=l (note 4) x x tempo rary sec t or group unprotect xxx v id hx a in (note 4) (note 4) high-z
12 am29lv640mh/l 26191f0 august 14, 2003 advance information word/byte configuration the byte# pin controls whether the device data i/o pins operate in the byte or word configuration. if the byte# pin is se t at logic ?1?, the device is in word con- figuration, dq0?dq15 are active and controlled by ce# and oe#. if the byte# pin is set at logic ?0?, the device is in byte configuration, and only data i/o pins dq0?dq7 are active and co ntrolled by ce# and oe#. the data i/ o pins dq8?dq14 are tri-stated, and the dq15 pin is used as an input for the lsb (a-1) address function. ve rs a ti l e i o ? (v io ) control the versatileio? (v io ) control allows the host system to set the voltage levels that the device generates and tolerates on ce# and dq i/os to the same voltage level that is asserted on v io . see ?ordering information? on page 9 for v io op- tions on this device. for example, a v i/o of 1.65?3.6 volts allows for i/o at the 1.8 or 3 volt levels, driving and receiving signals to and from other 1.8 or 3 v devices on the same data bus. requirements for reading array data to read array data from the outputs, the system must drive the ce# and oe# pins to v il . ce# is the power control and selects the device. oe# is the output control and gates array data to the output pins. we# should remain at v ih . the internal state machine is set for reading array data upon device power-up, or after a hardware reset. this ensures that no spurious alteration of the memory content occurs during the power transition. no command is necessary in this mode to obtain array data. standard microprocessor read cycles that assert valid addresses on the device address inputs produce valid data on the device data outputs. the device remains enabled for read access until the command register contents are altered. see ?reading array data? for more information. refer to the ac read-only op- erations table for timing specifications and to figure 14 for the timing diagram. refer to the dc characteristics table for the active current specification on read- ing array data. page mode read the device is capable of fast page mode read and is compatible with the page mode mask rom read operation. this mode provides faster read access speed for random locations within a page. the page size of the device is 4 words/8 bytes. the appropriate page is selected by the higher address bits a(max)?a2. address bits a1?a0 in word mode (a1?a-1 in byte mode) determine the specific word within a page. this is an asynchro nous operation; the microprocessor sup- plies the specific word location. the random or initial page access is equal to t acc or t ce and subsequent page read accesses (as long as the locations specified by the microprocessor falls within that page) is equivalent to t pacc . when ce# is deasserted and reasserted for a subsequent access, the access time is t acc or t ce . fast page mode accesses are obtained by keeping the ?read-page addresses? constant and changing the ?intra-read page? addresses.
august 14, 2003 26191f0 am29lv640mh/l 13 advance information writing commands/command sequences to write a command or command sequence (which includes programming data to the device and erasing sectors of memory), the system must drive we# and ce# to v il , and oe# to v ih . the device features an unlock bypass mode to facilitate faster programming. once the device enters the unlock bypass mode, only two write cycles are re- quired to program a word or byte, instead of four. the ?word/byte program command sequence? section has details on programming data to the device using both standard and unlock bypass command sequences. an erase operation can erase one sector, multiple sectors, or the entire device. ta b l e 2 indicates the address space that each sector occupies. refer to the dc characteristics table for the active current specification for the write mode. the ac characteristics section contains timing specification tables and timing diagrams for write operations. write buffer write buffer programming allows the system to write a maximum of 16 words/32 bytes in one programming operation. this results in faster effective program- ming time than the standard programming algorithms. see ?write buffer? for more information. accelerated program operation the device offers accelerated program operations through the acc function. this is one of two functions provided by the wp#/acc pin. this function is primarily intended to allow faster manufact uring throughput at the factory. if the system asserts v hh on this pin, the device automatically enters the afore- mentioned unlock bypass mode, temporarily unprotects any protected sectors, and uses the higher voltage on the pin to reduce the time required for program operations. the system would use a two-cycle program command sequence as required by the unlock bypass mode. removing v hh from the wp#/acc pin re- turns the device to normal operation. note that the wp#/acc pin must not be at v hh for operations other than accelerated programming, or device damage may result. in addition, no external pullup is necessary since the wp#/acc pin has internal pullup to v cc. autoselect functions if the system writes the autoselect comma nd sequence, the device enters the au- toselect mode. the system can then read autoselect codes from the internal register (which is separate from the memory array) on dq7?dq0. standard read cycle timings apply in this mode. refer to the autoselect mode and autoselect command sequence sections for more information.
14 am29lv640mh/l 26191f0 august 14, 2003 advance information standby mode when the system is not reading or writing to the device, it can place the device in the standby mode. in this mode, current consumption is greatly reduced, and the outputs are placed in the high impedance state, independent of the oe# input. the device enters the cmos standby mode when the ce# and reset# pins are both held at v io 0.3 v. (note that this is a more restricted voltage range than v ih .) if ce# and reset# are held at v ih , but not within v io 0.3 v, the device will be in the standby mode, but the standby current will be greater. the device requires standard access time (t ce ) for read access when the device is in either of these standby modes, before it is ready to read data. if the device is deselected during erasure or programming, the device draws ac- tive current until the operation is completed. refer to the dc characteristics table for the standby current specification. automatic sleep mode the automatic sleep mode minimizes flash device energy consumption. the de- vice automatically enables this mode when addresses remain stable for t acc + 30 ns. the automatic sleep mode is independent of the ce#, we#, and oe# con- trol signals. standard address access timings provide new data when addresses are changed. while in sleep mode, output data is latched and always available to the system. refer to the dc characteristics table for the automatic sleep mode current specification. reset#: hardware reset pin the reset# pin provides a hardware method of resetting the device to reading array data. when the reset# pin is driv en low for at least a period of t rp , the device immediately terminates any operation in progress, tristates all output pins, and ignores all read/write commands for the duration of the reset# pulse. the device also resets the internal stat e machine to reading array data. the op- eration that was interrupted should be reinitiated once the device is ready to accept another command sequence, to ensure data integrity. current is reduced for the duration of the reset# pulse. when reset# is held at v ss 0.3 v, the device draws cmos standby current (i cc4 ). if reset# is held at v il but not within v ss 0.3 v, the standby current will be greater. the reset# pin may be tied to the system reset circuitry. a system reset would thus also reset the flash memory, enabling the system to read the boot-up firm- ware from the flash memory. refer to the ac characteristics tables for reset# parameters and to figure 16 for the timing diagram. output disable mode when the oe# input is at v ih , output from the device is disabled. the output pins are placed in the high impedance state.
august 14, 2003 26191f0 am29lv640mh/l 15 advance information sector a21?a15 sector size (kbytes/ kwords) 8-bit address range (in hexadecimal) 16-bit address range (in hexadecimal) sa0 0000000 64/32 000000?00 ffff 0000 00?007fff sa1 0000001 64/32 010000?01 ffff 008000?00ffff sa2 0000010 64/32 020000?02 ffff 0100 00?017fff sa3 0000011 64/32 030000?03 ffff 018000?01ffff sa4 0000100 64/32 040000?04 ffff 0200 00?027fff sa5 0000101 64/32 050000?05 ffff 028000?02ffff sa6 0000110 64/32 060000?06 ffff 0300 00?037fff sa7 0000111 64/32 070000?07 ffff 038000?03ffff sa8 0001000 64/32 080000?08 ffff 0400 00?047fff sa9 0001001 64/32 090000?09 ffff 048000?04ffff sa10 0001010 64/32 0a0000?0affff 050000?057fff sa11 0001011 64/32 0b0000?0b ffff 058000?05ffff sa12 0001100 64/32 0c0000?0cffff 060000?067fff sa13 0001101 64/32 0d0000?0dffff0680 00?06ffff sa14 0001110 64/32 0e0000?0effff 070000?077fff sa15 0001111 64/32 0f0000?0fffff0780 00?07ffff sa16 0010000 64/32 100000?10 ffff 0800 00?087fff sa17 0010001 64/32 110000?11 ffff 088000?08ffff sa18 0010010 64/32 120000?12 ffff 0900 00?097fff sa19 0010011 64/32 130000?13 ffff 098000?09ffff sa20 0010100 64/32 140000?14 ffff 0a0000?0a7fff sa21 0010101 64/32 150000?15 ffff 0a8000?0affff sa22 0010110 64/32 160000?16 ffff 0b0000?0b7fff sa23 0010111 64/32 170000?17 ffff 0b8000?0bffff sa24 0011000 64/32 180000?18 ffff 0c0000?0c7fff sa25 0011001 64/32 190000?19 ffff 0c8000?0cffff sa26 0011010 64/32 1a0000?1affff0d0000?0d7fff sa27 0011011 64/32 1b0000?1b ffff 0d8000?0dffff sa28 0011100 64/32 1c0000?1cffff0e0000?0e7fff sa29 0011101 64/32 1d0000?1dffff0e80 00?0effff sa30 0011110 64/32 1e0000?1effff0f0000?0f7fff sa31 0011111 64/32 1f0000?1fffff0f80 00?0fffff sa32 0100000 64/32 200000?20 ffff 1000 00?107fff sa33 0100001 64/32 210000?21 ffff 108000?10ffff sa34 0100010 64/32 220000?22 ffff 1100 00?117fff
16 am29lv640mh/l 26191f0 august 14, 2003 advance information sa35 0100011 64/32 230000?23 ffff 118000?11ffff sa36 0100100 64/32 240000?24 ffff 1200 00?127fff sa37 0100101 64/32 250000?25 ffff 128000?12ffff sa38 0100110 64/32 260000?26 ffff 1300 00?137fff sa39 0100111 64/32 270000?27 ffff 138000?13ffff sa40 0101000 64/32 280000?28 ffff 1400 00?147fff sa41 0101001 64/32 290000?29 ffff 148000?14ffff sa42 0101010 64/32 2a0000?2affff 150000?157fff sa43 0101011 64/32 2b0000?2b ffff 158000?15ffff sa44 0101100 64/32 2c0000?2cffff 160000?167fff sa45 0101101 64/32 2d0000?2dffff1680 00?16ffff sa46 0101110 64/32 2e0000?2effff 170000?177fff sa47 0101111 64/32 2f0000?2fffff1780 00?17ffff sa48 0110000 64/32 300000?30 ffff 1800 00?187fff sa49 0110001 64/32 310000?31 ffff 188000?18ffff sa50 0110010 64/32 320000?32 ffff 1900 00?197fff sa51 0110011 64/32 330000?33 ffff 198000?19ffff sa52 0110100 64/32 340000?34 ffff 1a0000?1a7fff sa53 0110101 64/32 350000?35 ffff 1a8000?1affff sa54 0110110 64/32 360000?36 ffff 1b0000?1b7fff sa55 0110111 64/32 370000?37 ffff 1b8000?1bffff sa56 0111000 64/32 380000?38 ffff 1c0000?1c7fff sa57 0111001 64/32 390000?39 ffff 1c8000?1cffff sa58 0111010 64/32 3a0000?3affff1d0000?1d7fff sa59 0111011 64/32 3b0000?3b ffff 1d8000?1dffff sa60 0111100 64/32 3c0000?3cffff1e0000?1e7fff sa61 0111101 64/32 3d0000?3dffff1e80 00?1effff sa62 0111110 64/32 3e0000?3effff1f0000?1f7fff sa63 0111111 64/32 3f0000?3fffff1f80 00?1fffff sa64 1000000 64/32 400000?40 ffff 2000 00?207fff sa65 1000001 64/32 410000?41 ffff 208000?20ffff sa66 1000010 64/32 420000?42 ffff 2100 00?217fff sa67 1000011 64/32 430000?43 ffff 218000?21ffff sa68 1000100 64/32 440000?44 ffff 2200 00?227fff sa69 1000101 64/32 450000?45 ffff 228000?22ffff sa70 1000110 64/32 460000?46 ffff 2300 00?237fff sector a21?a15 sector size (kbytes/ kwords) 8-bit address range (in hexadecimal) 16-bit address range (in hexadecimal)
august 14, 2003 26191f0 am29lv640mh/l 17 advance information sa71 1000111 64/32 470000?47 ffff 238000?23ffff sa72 1001000 64/32 480000?48 ffff 2400 00?247fff sa73 1001001 64/32 490000?49 ffff 248000?24ffff sa74 1001010 64/32 4a0000?4affff 250000?257fff sa75 1001011 64/32 4b0000?4b ffff 258000?25ffff sa76 1001100 64/32 4c0000?4cffff 260000?267fff sa77 1001101 64/32 4d0000?4dffff2680 00?26ffff sa78 1001110 64/32 4e0000?4effff 270000?277fff sa79 1001111 64/32 4f0000?4fffff2780 00?27ffff sa80 1010000 64/32 500000?50 ffff 2800 00?287fff sa81 1010001 64/32 510000?51 ffff 288000?28ffff sa82 1010010 64/32 520000?52 ffff 2900 00?297fff sa83 1010011 64/32 530000?53 ffff 298000?29ffff sa84 1010100 64/32 540000?54 ffff 2a0000?2a7fff sa85 1010101 64/32 550000?55 ffff 2a8000?2affff sa86 1010110 64/32 560000?56 ffff 2b0000?2b7fff sa87 1010111 64/32 570000?57 ffff 2b8000?2bffff sa88 1011000 64/32 580000?58 ffff 2c0000?2c7fff sa89 1011001 64/32 590000?59 ffff 2c8000?2cffff sa90 1011010 64/32 5a0000?5affff2d0000?2d7fff sa91 1011011 64/32 5b0000?5b ffff 2d8000?2dffff sa92 1011100 64/32 5c0000?5cffff2e0000?2e7fff sa93 1011101 64/32 5d0000?5dffff2e80 00?2effff sa94 1011110 64/32 5e0000?5effff2f0000?2f7fff sa95 1011111 64/32 5f0000?5fffff2f80 00?2fffff sa96 1100000 64/32 600000?60 ffff 3000 00?307fff sa97 1100001 64/32 610000?61 ffff 308000?30ffff sa98 1100010 64/32 620000?62 ffff 3100 00?317fff sa99 1100011 64/32 630000?63 ffff 318000?31ffff sa100 1100100 64/32 640000?64 ffff 3200 00?327fff sa101 1100101 64/32 650000?65 ffff 328000?32ffff sa102 1100110 64/32 660000?66 ffff 3300 00?337fff sa103 1100111 64/32 670000?67 ffff 338000?33ffff sa104 1101000 64/32 680000?68 ffff 3400 00?347fff sa105 1101001 64/32 690000?69 ffff 348000?34ffff sa106 1101010 64/32 6a0000?6affff 350000?357fff sector a21?a15 sector size (kbytes/ kwords) 8-bit address range (in hexadecimal) 16-bit address range (in hexadecimal)
18 am29lv640mh/l 26191f0 august 14, 2003 advance information note: the address range is a21:a-1 in byte mode (byte# = v il ) or a21:a0 in word mode (byte# = v ih ). sa107 1101011 64/32 6b0000?6b ffff 358000?35ffff sa108 1101100 64/32 6c0000?6cffff 360000?367fff sa109 1101101 64/32 6d0000?6dffff3680 00?36ffff sa110 1101110 64/32 6e0000?6effff 370000?377fff sa111 1101111 64/32 6f0000?6fffff3780 00?37ffff sa112 1110000 64/32 700000?70 ffff 3800 00?387fff sa113 1110001 64/32 710000?71 ffff 388000?38ffff sa114 1110010 64/32 720000?72 ffff 3900 00?397fff sa115 1110011 64/32 730000?73 ffff 398000?39ffff sa116 1110100 64/32 740000?74 ffff 3a0000?3a7fff sa117 1110101 64/32 750000?75 ffff 3a8000?3affff sa118 1110110 64/32 760000?76 ffff 3b0000?3b7fff sa119 1110111 64/32 770000?77 ffff 3b8000?3bffff sa120 1111000 64/32 780000?78 ffff 3c0000?3c7fff sa121 1111001 64/32 790000?79 ffff 3c8000?3cffff sa122 1111010 64/32 7a0000?7affff3d0000?3d7fff sa123 1111011 64/32 7b0000?7b ffff 3d8000?3dffff sa124 1111100 64/32 7c0000?7cffff3e0000?3e7fff sa125 1111101 64/32 7d0000?7dffff3e80 00?3effff sa126 1111110 64/32 7e0000?7effff3f0000?3f7fff sa127 1111111 64/32 7f0000?7fffff3f80 00?3fffff sector a21?a15 sector size (kbytes/ kwords) 8-bit address range (in hexadecimal) 16-bit address range (in hexadecimal)
august 14, 2003 26191f0 am29lv640mh/l 19 advance information autoselect mode the autoselect mode provides manufacturer and device identification, and sector protection verification, through identifier codes output on dq7?dq0. this mode is primarily intended for programming eq uipment to automatically match a device to be programmed with its corresponding programming algorithm. however, the autoselect codes can also be accessed in-system through the command register. when using programming equipment, the autoselect mode requires v id on ad- dress pin a9. address pins a6, a3, a2, a1, and a0 must be as shown in tab l e 3 . in addition, when verifying sector protection, the sector address must appear on the appropriate highest order address bits (see tab l e 2 ). ta b l e 3 shows the re- maining address bits that are don?t care. when all necessary bits have been set as required, the programming equipment may then read the corresponding iden- tifier code on dq7?dq0. to access the autoselect codes in-system, the host system can issue the autose- lect command via the command register, as shown in tables 10 and 11 . this method does not require v id . refer to the autoselect command sequence section for more information. ta b l e 2 . autoselect codes, (high voltage method) legend: l = logic low = v il , h = logic high = v ih , sa = sector address, x = don?t care. sector group protection and unprotection the hardware sector group protection feature disables both program and erase operations in any sector group. in this device, a sector group consists of four ad- jacent sectors that are protected or unprotected at the same time (see ta b l e 4 ). the hardware sector group unprotection feature re-enables both program and erase operations in previously protected sector groups. sector group protection/ unprotection can be implemented via two methods. sector protection/unprotection requires v id on the reset# pin only, and can be implemented either in-system or via programming equipment. figure 2 shows the algorithms and figure 24 shows the timing diagram. this method uses stan- dard microprocessor bus cycle timing. for sector group unprotect, all unprotected sector groups must first be protected prior to the first sector group unprotect write cycle. description ce# oe# we # a21 to a15 a14 to a10 a9 a8 to a7 a6 a5 to a4 a3 to a2 a1 a0 dq8 to dq15 dq7 to dq0 byte# = v ih byte# = v il manufacturer id : amd l l h x x v id xl x l l l 00 x 01h device id cycle 1 llhxxv id xl x llh 22 x 7eh cycle 2 hh l 22 x 0ch cycle 3 hhh 22 x 01h sector protection verification llhsaxv id xl x l h l x x 01h (protected), 00h (unprotected) secsi sector indicator bit (dq7), wp# protects highest address sector llhxxv id xl x l h h x x 98h (factory locked), 18h (not factory locked) secsi sector indicator bit (dq7), wp# protects lowest address sector llhxxv id xl x l h h x x 88h (factory locked), 08h (not factory locked)
20 am29lv640mh/l 26191f0 august 14, 2003 advance information the device is shipped with all sector groups unprotected. amd offers the option of programming and protecting sector groups at its factory prior to shipping the device through amd?s expressflash? service. contact an amd representative for details. it is possible to determine whether a sector group is protected or unprotected. see the autoselect mode section for details. ta b l e 3 . sector group protection/unprotection address ta b l e sector group a21?a15 sa0 0000000 sa1 0000001 sa2 0000010 sa3 0000011 sa4?sa7 00001xx sa8?sa11 00010xx sa12?sa15 00011xx sa16?sa19 00100xx sa20?sa23 00101xx sa24?sa27 00110xx sa28?sa31 00111xx sa32?sa35 01000xx sa36?sa39 01001xx sa40?sa43 01010xx sa44?sa47 01011xx sa48?sa51 01100xx sa52?sa55 01101xx sa56?sa59 01110xx sa60?sa63 01111xx sa64?sa67 10000xx sa68?sa71 10001xx sa72?sa75 10010xx sa76?sa79 10011xx sa80?sa83 10100xx sa84?sa87 10101xx sa88?sa91 10110xx sa92?sa95 10111xx sa96?sa99 11000xx sa100?sa103 11001xx sa104?sa107 11010xx sa108?sa111 11011xx sa112?sa115 11100xx sa116?sa119 11101xx sa120?sa123 11110xx sa124 1111100 sa125 1111101 sa126 1111110 sa127 1111111
august 14, 2003 26191f0 am29lv640mh/l 21 advance information write protect (wp#) the write protect function provides a hardware method of protecting the first or last sector without using v id . write protect is one of two functions provided by the wp#/acc input. if the system asserts v il on the wp#/acc pin, the device disables program and erase functions in the first or last sector independently of whether those sectors were protected or unprotected using the method described in ?sector group pro- tection and unprotection?. note that if wp#/acc is at v il when the device is in the standby mode, the maximum input load current is increased. see the table in ?dc characteristics?. if the system asserts v ih on the wp#/acc pin, the device reverts to whether the first or last sector was previously set to be protected or unprotected using the method described in ?sector group protection and unprotection?. note: no exter- nal pullup is necessary since the wp#/acc pin has internal pullup to v cc . temporary sector group unprotect ( note: in this device, a sector group consists of four adjacent sectors that are pro- tected or unprotected at the same time (see table 4 ). this feature allows temporary unprotection of previously protected sector groups to change data in-system. the sector group unprotect mode is activated by set- ting the reset# pin to v id . during this mode, formerly protected sector groups can be programmed or erased by selecting the sector group addresses. once v id is removed from the reset# pin, all the previously protected sector groups are protected again. figure 1 shows the algorithm, and figure 23 shows the timing diagrams, for this feature. notes: 1. all protected sector groups unprotected (if wp# = v il , the first or last sector will remain protected). 2. all previously protected sector groups are protected once again. figure 1. temporary sector group unprotect operation start perform erase or program operations reset# = v ih temporary sector group unprotect completed (note 2) reset# = v id (note 1)
22 am29lv640mh/l 26191f0 august 14, 2003 advance information figure 2. in-system sector group protect/unprotect algorithms sector group protect: write 60h to sector group address with a6?a0 = 0xx0010 set up sector group address wait 150 s verify sector group protect: write 40h to sector group address with a6?a0 = 0xx0010 read from sector group address with a6?a0 = 0xx0010 start plscnt = 1 reset# = v id wait 1 ms first write cycle = 60h? data = 01h? remove v id from reset# write reset command sector group protect complete yes yes no plscnt = 25? yes device failed increment plscnt temporary sector group unprotect mode no sector group unprotect: write 60h to sector group address with a6?a0 = 1xx0010 set up first sector group address wait 15 ms verify sector group unprotect: write 40h to sector group address with a6?a0 = 1xx0010 read from sector group address with a6?a0 = 1xx0010 start plscnt = 1 reset# = v id wait 1 ms data = 00h? last sector group verified? remove v id from reset# write reset command sector group unprotect complete yes no plscnt = 1000? yes device failed increment plscnt temporary sector group unprotect mode no all sector groups protected? yes protect all sector groups: the indicated portion of the sector group protect algorithm must be performed for all unprotected sector groups prior to issuing the first sector group unprotect address set up next sector group address no yes no yes no no yes no sector group protect algorithm sector group unprotect algorithm first write cycle = 60h? protect another sector group? reset plscnt = 1
august 14, 2003 26191f0 am29lv640mh/l 23 advance information secsi (secured silicon) sector flash memory region the secsi (secured silicon) sector featur e provides a flash memory region that enables permanent part identification through an electronic serial number (esn). the secsi sector is 128 words/256 bytes in length, and uses a secsi sec- tor indicator bit (dq7) to indicate whether or not the secsi sector is locked when shipped from the factory. this bit is permanently set at the factory and cannot be changed, which prevents cloning of a fact ory locked part. this ensures the secu- rity of the esn once the product is shipped to the field. amd offers the device with the secsi sector either factory locked or customer lockable. the factory-locked version is al ways protected when shipped from the factory, and has the secsi (secured silicon) sector indicator bit permanently set to a ?1.? the customer-lockable version is shipped with the secsi sector unpro- tected, allowing customers to program the sector after receiving the device. the customer-lockable version also has the secsi sector indicator bit permanently set to a ?0.? thus, the secsi sector indicator bit prevents customer-lockable de- vices from being used to replace devices that are factory locked. the secsi sector address space in this device is allocated as follows: the system accesses the secsi sector through a command sequence (see ?enter secsi sector/exit secsi sector command sequence?). after the system has writ- ten the enter secsi sector command sequence, it may read the secsi sector by using the addresses normally occupied by the first sector (sa0). this mode of op- eration continues until the system issues the exit secsi sector command sequence, or until power is removed from the device. on power-up, or following a hardware reset, the de vice reverts to sending commands to sector sa0. factory locked: secsi sector programmed and protected at the factory in devices with an esn, the secsi sector is protected when the device is shipped from the factory. the secsi sector cannot be modified in any way. see ta b l e 5 for secsi sector addressing. customers may opt to have their code programmed by amd through the amd ex- pressflash service. the devices are then shipped from amd?s factory with the secsi sector permanently locked. contact an amd representative for details on using amd?s expressflash service. customer lockable: secsi sector not programmed or protected at the factory as an alternative to the factory-locked version, the device may be ordered such that the customer may program and protect the 128-word/256 bytes secsi sec- tor. see ta b l e 5 for secsi sector addressing. the system may program the secsi sector using the write-buffer, accelerated and/or unlock bypass methods, in addition to the standard programming com- mand sequence. see command definitions . secsi sector address range standard factory locked expressflash factory locked customer lockable x16 x8 000000h? 000007h 000000h? 00000fh esn esn or determined by customer determined by customer 000008h? 00007fh 000010h? 0000ffh unavailable determined by customer
24 am29lv640mh/l 26191f0 august 14, 2003 advance information programming and protecting the secsi sector must be used with caution since, once protected, there is no procedure available for unprotecting the secsi sector area and none of the bits in the secsi sector memory space can be modified in any way. the secsi sector area can be protected using one of the following procedures: ? write the three-cycle enter secsi sector region command sequence, and then follow the in-system sector protect algorithm as shown in figure 2, ex- cept that reset# may be at either v ih or v id . this allows in-system protec- tion of the secsi sector without raising any device pin to a high voltage. note that this method is only applicable to the secsi sector. ? to verify the protect/unprotect status of the secsi sector, follow the algo- rithm shown in figure 3. once the secsi sector is programmed, locked and verified, the system must write the exit secsi sector region command sequence to return to reading and writing within the remainder of the array. figure 3. secsi sector protect verify hardware data protection the command sequence requirement of unlock cycles for programming or erasing provides data protection against in advertent writes (refer to tables 10 and 11 for command definitions). in addition, the following hardware data protection mea- sures prevent accidental erasure or programming, which might otherwise be caused by spurious system level signals during v cc power-up and power-down transitions, or from system noise. low v cc write inhibit when v cc is less than v lko , the device does not accept any write cycles. this pro- tects data during v cc power-up and power-down. the command register and all internal program/erase circuits are disabled, and the device resets to the read mode. subsequent writes are ignored until v cc is greater than v lko . the system write 60h to any address write 40h to secsi sector address with a6 = 0, a1 = 1, a0 = 0 start reset# = v ih or v id wait 1 ms read from secsi sector address with a6 = 0, a1 = 1, a0 = 0 if data = 00h, secsi sector is unprotected. if data = 01h, secsi sector is protected. remove v ih or v id from reset# write reset command secsi sector protect verify complete
august 14, 2003 26191f0 am29lv640mh/l 25 advance information must provide the proper signals to the control pins to prevent unintentional writes when v cc is greater than v lko . write pulse ?glitch? protection noise pulses of less than 5 ns (typical) on oe#, ce# or we# do not initiate a write cycle. logical inhibit write cycles are inhibited by holding any one of oe# = v il , ce# = v ih or we# = v ih . to initiate a write cycle, ce# and we# must be a logical zero while oe# is a logical one. power-up write inhibit if we# = ce# = v il and oe# = v ih during power up, the device does not accept commands on the rising edge of we#. the internal state machine is automatically reset to the read mode on power-up. common flash memory interface (cfi) the common flash interface (cfi) specificati on outlines device and host system software interrogation handshake, which allows specific vendor-specified soft- ware algorithms to be used for entire families of devices. software support can then be device-independent, jedec id-independent, and forward- and back- ward-compatible for the specified flash device families. flash vendors can standardize their existing interfaces for long-term compatibility. this device enters the cfi query mode when the system writes the cfi query command, 98h, to address 55h, any time the device is ready to read array data. the system can read cfi information at the addresses given in tables 6 ? 9 . to ter- minate reading cfi data, the system must write the reset command. the system can also write the cfi query command when the device is in the au- toselect mode. the device enters the cfi query mode, and the system can read cfi data at the addresses given in tables 6 ? 9 . the system must write the reset command to return the device to reading array data. for further information, please refer to the cfi specification and cfi publication 100, available via the world wide web at http://www.amd.com/flash/cfi. alter- natively, contact a sales office or representative for copies of these documents.
26 am29lv640mh/l 26191f0 august 14, 2003 advance information ta b l e 4 . cfi query identification string table 5. system interface string addresses (x16) addresses (x8) data description 10h 11h 12h 20h 22h 24h 0051h 0052h 0059h query unique ascii string ?qry? 13h 14h 26h 28h 0002h 0000h primary oem command set 15h 16h 2ah 2ch 0040h 0000h address for primary extended table 17h 18h 2eh 30h 0000h 0000h alternate oem command set (00h = none exists) 19h 1ah 32h 34h 0000h 0000h address for alternate oem extended table (00h = none exists) addresses (x16) addresses (x8) data description 1bh 36h 0027h v cc min. (write/erase) d7?d4: volt, d3?d0: 100 millivolt 1ch 38h 0036h v cc max. (write/erase) d7?d4: volt, d3?d0: 100 millivolt 1dh 3ah 0000h v pp min. voltage (00h = no v pp pin present) 1eh 3ch 0000h v pp max. voltage (00h = no v pp pin present) 1fh 3eh 0007h typical timeout per single byte/word write 2 n s 20h 40h 0007h typical timeout for min. size buffer write 2 n s (00h = not supported) 21h 42h 000ah typical timeout per individual block erase 2 n ms 22h 44h 0000h typical timeout for full chip erase 2 n ms (00h = not supported) 23h 46h 0001h max. timeout for byte/word write 2 n times typical 24h 48h 0005h max. timeout for buffer write 2 n times typical 25h 4ah 0004h max. timeout per individual block erase 2 n times typical 26h 4ch 0000h max. timeout for full chip erase 2 n times typical (00h = not supported)
august 14, 2003 26191f0 am29lv640mh/l 27 advance information ta b l e 6 . device geometry definition addresses (x16) addresses (x8) data description 27h 4eh 0017h device size = 2 n byte 28h 29h 50h 52h 0002h 0000h flash device interface descriptio n (refer to cfi publication 100) 2ah 2bh 54h 56h 0005h 0000h max. number of byte in multi-byte write = 2 n (00h = not supported) 2ch 58h 0001h number of erase block regions within de vice (01h = uniform device, 02h = boot device) 2dh 2eh 2fh 30h 5ah 5ch 5eh 60h 007fh 0000h 0000h 0001h erase block region 1 information (refer to the cfi specification or cfi publication 100) 31h 32h 33h 34h 62h 64h 66h 68h 0000h 0000h 0000h 0000h erase block region 2 information (refer to cfi publication 100) 35h 36h 37h 38h 6ah 6ch 6eh 70h 0000h 0000h 0000h 0000h erase block region 3 information (refer to cfi publication 100) 39h 3ah 3bh 3ch 72h 74h 76h 78h 0000h 0000h 0000h 0000h erase block region 4 information (refer to cfi publication 100)
28 am29lv640mh/l 26191f0 august 14, 2003 advance information ta b l e 7 . primary vendor-specific extended query command definitions writing specific address and data commands or sequences into the command register initiates device operations. tables 10 and 11 define the valid register command sequences. writing incorrect address and data values or writing them in the improper sequence may place the device in an unknown state. a reset command is then required to retu rn the device to reading array data. all addresses are latched on the falling edge of we# or ce#, whichever happens later. all data is latched on the rising edge of we# or ce#, whichever happens first. refer to the ac characteristics section for timing diagrams. addresses (x16) addresses (x8) data description 40h 41h 42h 80h 82h 84h 0050h 0052h 0049h query-unique ascii string ?pri? 43h 86h 0031h major version number, ascii 44h 88h 0033h minor version number, ascii 45h 8ah 0008h address sensitive unlock (bits 1-0) 0 = required, 1 = not required process technology (bits 7-2) 0010b = 0.23 m mirrorbit 46h 8ch 0002h erase suspend 0 = not supported, 1 = to read only, 2 = to read & write 47h 8eh 0001h sector protect 0 = not supported, x = number of sectors in per group 48h 90h 0001h sector temporary unprotect 00 = not supported, 01 = supported 49h 92h 0004h sector protect/unprotect scheme 04 = 29lv800 mode 4ah 94h 0000h simultaneous operation 00 = not supported, x = number of sectors in bank 4bh 96h 0000h burst mode type 00 = not supported, 01 = supported 4ch 98h 0001h page mode type 00 = not supported, 01 = 4 word/8 byte page, 02 = 8 word/16 byte page 4dh 9ah 00b5h acc (acceleration) supply minimum 00h = not supported, d7-d4: volt, d3-d0: 100 mv 4eh 9ch 00c5h acc (acceleration) supply maximum 00h = not supported, d7-d4: volt, d3-d0: 100 mv 4fh 9eh 0004h/ 0005h top/bottom boot sector flag 00h = uniform device without wp# protect, 02h = bottom boot device, 03h = top boot device, 04h = uniform sector s bottom wp# protect, 05h = uniform sectors top wp# protect 50h a0h 0001h program suspend 00h = not supported, 01h = supported
august 14, 2003 26191f0 am29lv640mh/l 29 advance information reading array data the device is automatically set to reading array data after device power-up. no commands are required to retrieve data. the device is ready to read array data after completing an embedded prog ram or embedded erase algorithm. after the device accepts an erase susp end command, the device enters the erase-suspend-read mode, after which the system can read data from any non- erase-suspended sector. after completing a programming operation in the erase suspend mode, the system may once again read array data with the same ex- ception. see the erase suspend/erase resume commands section for more information. the system must issue the reset command to return the device to the read (or erase-suspend-read) mode if dq5 goes high during an active program or erase operation, or if the device is in the autoselect mode. see the next section, reset command , for more information. see also requirements for reading array data in the device bus operations sec- tion for more information. the read-only operations table provides the read parameters, and figure 14 shows the timing diagram. reset command writing the reset command resets the dev ice to the read or erase-suspend-read mode. address bits are don?t cares for this command. the reset command may be written between the sequence cycles in an erase command sequence before erasing begins. this resets the device to the read mode. once erasure begins, however, the device ignores reset commands until the operation is complete. the reset command may be written between the sequence cycles in a program command sequence before programming begins. this resets the device to the read mode. if the program command sequence is written while the device is in the erase suspend mode, writing the reset command returns the device to the erase-suspend-read mode. once programming begins, however, the device ig- nores reset commands until the operation is complete. the reset command may be written between the sequence cycles in an autoselect command sequence. once in the autosele ct mode, the reset command must be written to return to the read mode. if the device entered the autoselect mode while in the erase suspend mode, writin g the reset command returns the device to the erase-suspend-read mode. if dq5 goes high during a program or erase operation, writing the reset command returns the device to the read mode (or erase-suspend-read mode if the device was in erase suspend). note that if dq1 goes high during a write buffer programming operation, the sys- tem must write the write-to-buffer-abor t reset command sequence to reset the device for the next operation.
30 am29lv640mh/l 26191f0 august 14, 2003 advance information autoselect command sequence the autoselect command sequence allows the host system to read several iden- tifier codes at specific addresses: note: the device id is read over three cycles. sa = sector address ta b l e s 10 and 11 show the address requirements and codes. this method is an alternative to that shown in ta b l e 3 , which is intended for prom programmers and requires v id on address pin a9. the autoselect command sequence may be written to an address that is either in the read or erase-suspend-read mode. the autoselect command may not be written while the device is actively programming or erasing. the autoselect command sequence is initiated by first writing two unlock cycles. this is followed by a third write cycle th at contains the autoselect command. the device then enters the autoselect mode. the system may read at any address any number of times without initiating another autoselect command sequence: the system must write the reset command to return to the read mode (or erase- suspend-read mode if the device was previously in erase suspend). enter secsi sector/exit secsi sector command sequence the secsi sector region provides a secured data area containing an 8-word/16- byte random electronic serial number (esn). the system can access the secsi sector region by issuing the three-cycle enter secsi sector command sequence. the device continues to access the secsi sector region until the system issues the four-cycle exit secsi sector comman d sequence. the exit secsi sector com- mand sequence returns the device to normal operation. tables 10 and 11 show the address and data requirements for bo th command sequences. see also ?secsi (secured silicon) sector flash memory region? for further information. note that the acc function and unlock bypass modes are not available when the secsi sec- tor is enabled. word/byte program command sequence programming is a four-bus-cycle operat ion. the program command sequence is initiated by writing two unlock write cycles, followed by the program set-up com- mand. the program address and data are written next, which in turn initiate the embedded program algorithm. the system is not required to provide further con- trols or timings. the device automatically provides internally generated program pulses and verifies the programmed cell margin. tables 10 and 11 show the ad- dress and data requirements for the word/byte program command sequence, respectively. when the embedded program algorithm is complete, the device then returns to the read mode and addresses are no longer latched. the system can determine identifier code a7:a0 (x16) a6:a-1 (x8) manufacturer id 00h 00h device id, cycle 1 01h 02h device id, cycle 2 0eh 1ch device id, cycle 3 0fh 1eh secsi sector factory protect 03h 06h sector protect verify (sa)02h (sa)04h
august 14, 2003 26191f0 am29lv640mh/l 31 advance information the status of the program operation by using dq7 or dq6. refer to the write op- eration status section for information on these status bits. any commands written to the device during the embedded program algorithm are ignored. note that a hardware reset immediately terminates the program operation. the program command sequence should be reinitiated once the device has returned to the read mode, to ensure data integrity. note that the acc func- tion and unlock bypass modes are not available when the secsi sector is enabled. programming is allowed in any sequence and across sector boundaries. a bit cannot be programmed from ?0? back to a ?1.? attempting to do so may cause the device to set dq5 = 1, or cause the dq7 and dq6 status bits to indicate the operation was successful. however, a succeeding read will show that the data is still ?0.? only erase operations can convert a ?0? to a ?1.? unlock bypass command sequence the unlock bypass feature allows the system to program words to the device faster than using the standard program command sequence. the unlock bypass command sequence is initiated by first writing two unlock cycles. this is followed by a third write cycle containing the unlock bypass command, 20h. the device then enters the unlock bypass mode. a two-cycle unlock bypass program com- mand sequence is all that is required to program in this mode. the first cycle in this sequence contains the unlock bypass program command, a0h; the second cycle contains the program address and data. additional data is programmed in the same manner. this mode dispenses with the initial two unlock cycles required in the standard program command sequence, resulting in faster total program- ming time. tables 10 and 11 show the requirements for the command sequence. during the unlock bypass mode, only the unlock bypass program and unlock by- pass reset commands are valid. to exit the unlock bypass mode, the system must issue the two-cycle unlock bypass reset command sequence. the first cycle must contain the data 90h. the second cycle must contain the data 00h. the de- vice then returns to the read mode. write buffer programming write buffer programming allows the system write to a maximum of 16 words/32 bytes in one programming operation. this results in faster effective program- ming time than the standard programming algorithms. the write buffer programming command sequence is initiated by first writing two unlock cycles. this is followed by a third write cycle co ntaining the write buffer load command written at the sector address in which programming will occur. the fourth cycle writes the sector address and the number of word locations, minus one, to be programmed. for example, if the system will program 6 unique address locations, then 05h should be written to the device. this tells the device how many write buffer addresses will be loaded with data and therefore when to expect the pro- gram buffer to flash command. the number of locations to program cannot exceed the size of the write buffer or the operation will abort. the fifth cycle writes the first address lo cation and data to be programmed. the write-buffer-page is selected by address bits a max ?a 4 . all subsequent address/ data pairs must fall within the selected-write-buffer-page. the system then writes the remaining address/data pairs in to the write buffer. write buffer loca- tions may be loaded in any order. the write-buffer-page address must be the same for all address/data pairs loaded into the write buffer. (this means write buffer programming cannot be performed
32 am29lv640mh/l 26191f0 august 14, 2003 advance information across multiple write-buffer pages. this also means that write buffer program- ming cannot be performed across multiple se ctors. if the system attempts to load programming data outside of the selected write-buffer page, the operation will abort. note that if a write buffer address location is loaded multiple times, the address/ data pair counter will be decremented for every data load operation. the host system must therefore account for loadin g a write-buffer location more than once. the counter decrements for each data load operation, not for each unique write-buffer-address location. note also that if an address location is loaded more than once into the buffer, the final data loaded for that address will be programmed. once the specified number of write buffer locations have been loaded, the system must then write the program buffer to fl ash command at the sector address. any other address and data combination aborts the write buffer programming oper- ation. the device then begins programming. data polling should be used while monitoring the last address location loaded into the write buffer. dq7, dq6, dq5, and dq1 should be monitored to determine the device status during write buffer programming. the write-buffer programming operation can be suspended using the standard program suspend/resume commands. upon successful completion of the write buffer programming operation, the device is ready to execute the next command. the write buffer programming sequence can be aborted in the following ways: ? load a value that is greater than the pa ge buffer size during the number of locations to program step. ? write to an address in a sector different than the one specified during the write-buffer-load command. ? write an address/data pair to a different write-buffer-page than the one se- lected by the starting address during the write buffer data loading stage of the operation. ? write data other than the confirm command after the specified number of data load cycles. the abort condition is indicated by dq1 = 1, dq7 = data# (for the last address location loaded), dq6 = toggle, and dq5=0. a write-to-buffer-abort reset com- mand sequence must be written to reset the device for the next operation. note that the full 3-cycle write-to-buffer-abort reset command sequence is required when using write-buffer-programming features in unlock bypass mode. accelerated program the device offers accelerated program operations through the wp#/acc pin. when the system asserts v hh on the wp#/acc pin, the device automatically en- ters the unlock bypass mode. the system may then write the two-cycle unlock bypass program command sequence. the device uses the higher voltage on the wp#/acc pin to accelerate the operation. note that the wp#/ acc pin must not be at v hh for operations other than accelerated programming, or device damage may result. in addition, no external pullup is necessary since the wp#/acc pin has internal pullup to v cc . figure 5 illustrates the algorithm for the program operation. refer to the erase and program operations table in the ac characteristics section for parameters, and figure 17 for timing diagrams.
august 14, 2003 26191f0 am29lv640mh/l 33 advance information figure 4. write buffer programming operation write ?write to buffer? command and sector address write number of addresses to program minus 1(wc) and sector address write program buffer to flash sector address write first address/data write to a different sector address fail or abort pass read dq7 - dq0 at last loaded address read dq7 - dq0 with address = last loaded address write next address/data pair wc = wc - 1 wc = 0 ? part of ?write to buffer? command sequence yes yes yes yes yes yes no no no no no no abort write to buffer operation? dq7 = data? dq7 = data? dq5 = 1? dq1 = 1? write to buffer aborted. must write ?write-to-buffer abort reset? command sequence to return to read mode. notes: 1. when sector address is specified, any address in the selected sector is acceptable. however, when loading write-buffer address locations with data, all addresses must fall within the selected write-buffer page. 2. dq7 may change simultaneously with dq5. therefore, dq7 should be verified. 3. if this flowchart location was reached because dq5= ?1?, then the device failed. if this flowchart location was reached because dq1= ?1?, then the write to buffer operation was aborted. in either case, the proper reset command must be written before the device can begin another operation. if dq1=1, write the write- buffer-programming-abort-reset command. if dq5=1, write the reset command. 4. see table 11 for command sequences required for write buffer programming. (note 1) (note 2) (note 3)
34 am29lv640mh/l 26191f0 august 14, 2003 advance information note: see table 11 for program command sequence. figure 5. program operation program suspend/program resume command sequence the program suspend command allows th e system to interrupt a programming operation or a write to buffer programming operation so that data can be read from any non-suspended sector. when the program suspend command is written during a programming process, the device halts the program operation within 15 s maximum (5 s typical) and updates the status bits. addresses are not re- quired when writing the program suspend command. after the programming operation has been suspended, the system can read array data from any non-suspended sector. the program suspend command may also be issued during a programming operation while an erase is suspended. in this case, data may be read from any addresses not in erase suspend or program suspend. if a read is needed from the secsi sector area (one-time program area), then user must use the proper co mmand sequences to enter and exit this region. note that the secsi sector, autoselect, and cfi functions are unavailable when an program operation is in progress. the system may also write the autosele ct command sequence when the device is in the program suspend mode. the system can read as many autoselect codes as required. when the device exits the autoselect mode, the device reverts to the program suspend mode, and is ready for another valid operation. see au- toselect command sequence for more information. start write program command sequence data poll from system verify data? no yes last address? no yes programming completed increment address embedded program algorithm in progress
august 14, 2003 26191f0 am29lv640mh/l 35 advance information after the program resume command is written, the device reverts to program- ming. the system can determine the status of the program operation using the dq7 or dq6 status bits, just as in the standard program operation. see write operation status for more information. the system must write the program resume command (address bits are don?t care) to exit the program suspend mode and continue the programming opera- tion. further writes of the resume command are ignored. another program suspend command can be written after the device has resume programming. figure 6. program suspend/program resume chip erase command sequence chip erase is a six bus cycle operation. the chip erase command sequence is ini- tiated by writing two unlock cycles, followed by a set-up command. two additional unlock write cycles are then followed by the chip erase command, which in turn invokes the embedded erase algorithm. the device does not require the system to preprogram prior to erase. the embedded erase algorithm auto- matically preprograms and verifies the entire memory for an all zero data pattern prior to electrical erase. the system is no t required to provide any controls or tim- ings during these operations. tables 10 and 11 show the address and data requirements for the chip erase command sequence. program operation or write-to-buffer sequence in progress write program suspend command sequence command is also valid for erase-suspended-program operations autoselect and secsi sector read operations are also allowed data cannot be read from erase- o r program-suspended sectors write program resume command sequence read data as required done reading? no yes write address/data xxxh/30h device reverts to operation prior to program suspend write address/data xxxh/b0h wait 15 ms
36 am29lv640mh/l 26191f0 august 14, 2003 advance information when the embedded erase algorithm is complete, the device returns to the read mode and addresses are no longer latche d. the system can determine the status of the erase operation by using dq7, dq6, or dq2. refer to the write operation status section for information on these status bits. any commands written during the chip erase operation are ignored. however, note that a hardware reset immediately terminates the erase operation. if that occurs, the chip erase command sequence should be reinitiated once the device has returned to reading array data, to ensure data integrity. note that the secsi sector, autoselect, and cfi functions are unavailable when an erase operation is in progress. figure 7 illustrates the algorithm for the erase operation. refer to the erase and program operations tables in the ac characteristics section for parameters, and figure 19 section for timing diagrams. sector erase command sequence sector erase is a six bus cycle operation. the sector erase command sequence is initiated by writing two unlock cycles, followed by a set-up command. two addi- tional unlock cycles are written, and are then followed by the address of the sector to be erased, and the sector erase command. tables 10 and 11 show the address and data requirements for the sector erase command sequence. the device does not require the system to preprogram prior to erase. the em- bedded erase algorithm automatically programs and verifies the entire memory for an all zero data pattern prior to electr ical erase. the system is not required to provide any controls or timings during these operations. after the command sequence is written, a sector erase time-out of 50 s occurs. during the time-out period, additional sector addresses and sector erase com- mands may be written. loading the sector erase buffer may be done in any sequence, and the number of sectors may be from one sector to all sectors. the time between these additional cycles must be less than 50 s, otherwise erasure may begin. any sector erase address and command following the exceeded time- out may or may not be accepted. it is recommended that processor interrupts be disabled during this time to ensure all commands are accepted. the interrupts can be re-enabled after the last sector erase command is written. any com- mand other than sector erase or erase suspend during the time-out period resets the device to the read mode. the system must rewrite the command sequence and any additional addresses and commands. note that the secsi sector, autoselect, and cfi functions are unavailable when an erase oper- ation is in progress. the system can monitor dq3 to determine if the sector erase timer has timed out (see the section on dq3: sector erase timer.). the time-out begins from the ris- ing edge of the final we# pulse in the command sequence. when the embedded erase algorithm is complete, the device returns to reading array data and addresses are no longer latched. the system can determine the status of the erase operation by reading dq7, dq6, or dq2 in the erasing sector. refer to the write operation status section for information on these status bits. once the sector erase operation has begun, only the erase suspend command is valid. all other commands are ignored. however, note that a hardware reset im- mediately terminates the erase operation. if that occurs, the sector erase command sequence should be reinitiated once the device has returned to reading array data, to ensure data integrity.
august 14, 2003 26191f0 am29lv640mh/l 37 advance information figure 7 illustrates the algorithm for the erase operation. refer to the erase and program operations tables in the ac characteristics section for parameters, and figure 19 section for timing diagrams. notes: 1. see tables 10 and 11 for erase command sequence. 2. see the section on dq3 for information on the sector erase timer. figure 7. erase operation erase suspend/erase resume commands the erase suspend command, b0h, allows the system to interrupt a sector erase operation and then read data from, or program data to, any sector not selected for erasure. this command is valid only during the sector erase operation, includ- ing the 50 s time-out period during the sector erase command sequence. the erase suspend command is ignored if written during the chip erase operation or embedded program algorithm. when the erase suspend command is written during the sector erase operation, the device requires a maximum of 20 (typical 5 s) to suspend the erase opera- tion. however, when the erase suspend command is written during the sector erase time-out, the device immediately terminates the time-out period and sus- pends the erase operation. after the erase operation has been suspen ded, the device enters the erase-sus- pend-read mode. the system can read data from or program data to any sector not selected for erasure. (the device ?erase suspends? all sectors selected for erasure.) reading at any address within erase-suspended sectors produces sta- tus information on dq7?dq0. the system can use dq7, or dq6 and dq2 together, to determine if a sector is actively erasing or is erase-suspended. refer to the write operation status section for information on these status bits. start write erase command sequence (notes 1, 2) data poll to erasing bank from system data = ffh? no yes erasure completed embedded erase algorithm in progress
38 am29lv640mh/l 26191f0 august 14, 2003 advance information after an erase-suspended program operation is complete, the device returns to the erase-suspend-read mode. the system can determine the status of the pro- gram operation using the dq7 or dq6 status bits, just as in the standard word program operation. refer to the write operation status section for more information. in the erase-suspend-read mode, the syst em can also issue the autoselect com- mand sequence. refer to the autoselect mode and autoselect command sequence sections for details. to resume the sector erase operation, the system must write the erase resume command. the address of the erase-suspended sector is required when writing this command. further writes of the re sume command are ignored. another erase suspend command can be written after the chip has resumed erasing.
august 14, 2003 26191f0 am29lv640mh/l 39 advance information command definitions table 8. command definitions (x16 mode, byte# = v ih ) command sequence (note 1) cycles bus cycles (notes 2?5) first second third fourth fifth sixth addr data addr data addr data addr data addr data addr data read (note 5) 1 ra rd reset (note 6) 1 xxx f0 autoselect (note 7) manufacturer id 4 555 aa 2aa 55 555 90 x00 0001 device id (note 8) 6 555 aa 2aa 55 555 90 x01 227e x0e 220c x0f 2201 secsi ? sector factory protect (note 9) 4 555 aa 2aa 55 555 90 x03 (note 10) sector group protect verify (note 10) 4 555 aa 2aa 55 555 90 (sa)x02 00/01 enter secsi sector region 3 555 aa 2aa 55 555 88 exit secsi sector region 4 555 aa 2aa 55 555 90 xxx 00 program 4 555 aa 2aa 55 555 a0 pa pd write to buffer (note 11) 6 555 aa 2aa 55 sa 25 sa wc pa pd wbl pd program buffer to flash 1 sa 29 write to buffer abort reset (note 12) 3 555 aa 2aa 55 555 f0 unlock bypass 3 555 aa 2aa 55 555 20 unlock bypass program (note 13) 2 xxx a0 pa pd unlock bypass reset (note 14) 2 xxx 90 xxx 00 chip erase 6 555 aa 2aa 55 555 80 555 aa 2aa 55 555 10 sector erase 6 555 aa 2aa 55 555 80 555 aa 2aa 55 sa 30 program/erase suspend (note 15) 1 xxx b0 program/erase resume (note 16) 1 xxx 30 cfi query (note 17) 1 55 98 legend: x = don?t care ra = read address of memory location to be read. rd = read data read from location ra during read operation. pa = program address . addresses latch on falling edge of we# or ce# pulse, whichever happens later. pd = program data for location pa. data latches on rising edge of we# or ce# pulse, whichever happens first. sa = sector address of sector to be verified (in autoselect mode) or erased. address bits a21?a15 uniquely select any sector. wbl = write buffer location. address must be within same write buffer page as pa. wc = word count. number of write buffer locations to load minus 1. notes: 1. see table 1 for description of bus operations. 2. all values are in hexadecimal. 3. shaded cells indicate read cycles. all others are write cycles. 4. during unlock and command cycles, when lower address bits are 555 or 2aa as shown in table, address bits above a11 and data bits above dq7 are don?t care. 5. no unlock or command cycles required when device is in read mode. 6. reset command is required to return to read mode (or to erase- suspend-read mode if previously in erase suspend) when device is in autoselect mode, or if dq5 goes high while device is providing status information. 7. fourth cycle of the autoselect command sequence is a read cycle. data bits dq15?dq8 are don?t care. except for rd, pd and wc. see autoselect command sequence section for more information. 8. device id must be read in three cycles. 9. if wp# protects highest address sector, data is 98h for factory locked and 18h for not factory locked. if wp# protects lowest address sector, data is 88h for factory locked and 08h for not factor locked. 10. data is 00h for an unprotected sector group and 01h for a protected sector group. 11. total number of cycles in command sequence is determined by number of words written to write buffer. maximum number of cycles in command sequence is 21. 12. command sequence resets device for next command after aborted write-to-buffer operation. 13. unlock bypass command is required prior to unlock bypass program command. 14. unlock bypass reset command is required to return to read mode when device is in unlock bypass mode. 15. system may read and program in non-erasing sectors, or enter autoselect mode, when in erase suspend mode. erase suspend command is valid only during a sector erase operation. 16. erase resume command is valid only during erase suspend mode. 17. command is valid when device is ready to read array data or when device is in autoselect mode.
40 am29lv640mh/l 26191f0 august 14, 2003 advance information table 9. command definitions (x8 mode, byte# = v il ) command sequence (note 1) cycles bus cycles (notes 2?5) first second third fourth fifth sixth addr data addr data addr data addr data addr data addr data read (note 6) 1 ra rd reset (note 7) 1 xxx f0 autoselect (note 8) manufacturer id 4 aaa aa 555 55 aaa 90 x00 01 device id (note 9) 6 aaa aa 555 55 aaa 90 x02 7e x1c 0c x1e 01 secsi ? sector factory protect (note 10) 4 aaa aa 555 55 aaa 90 x06 (note 10) sector group protect verify (note 11) 4 aaa aa 555 55 aaa 90 (sa)x04 00/01 enter secsi sector region 3 aaa aa 555 55 aaa 88 exit secsi sector region 4 aaa aa 555 55 aaa 90 xxx 00 program 4 aaa aa 555 55 aaa a0 pa pd write to buffer (note 12) 6 aaa aa 555 55 sa 25 sa bc pa pd wbl pd program buffer to flash 1 sa 29 write to buffer abort reset (note 13) 3 aaa aa 555 55 aaa f0 unlock bypass 3 aaa aa 555 55 aaa 20 unlock bypass program (note 14) 2 xxx a0 pa pd unlock bypass reset (note 15) 2 xxx 90 xxx 00 chip erase 6 aaa aa 555 55 aaa 80 aaa aa 555 55 aaa 10 sector erase 6 aaa aa 555 55 aaa 80 aaa aa 555 55 sa 30 program/erase suspend (note 16) 1 xxx b0 program/erase resume (note 17) 1 xxx 30 cfi query (note 18) 1 aa 98 legend: x = don?t care ra = read address of memory location to be read. rd = read data read from location ra during read operation. pa = program address . addresses latch on falling edge of we# or ce# pulse, whichever happens later. pd = program data for location pa. data latches on rising edge of we# or ce# pulse, whichever happens first. sa = sector address of sector to be verified (in autoselect mode) or erased. address bits a21?a15 uniquely select any sector. wbl = write buffer location. address must be within same write buffer page as pa. bc = byte count. number of write buffer locations to load minus 1. notes: 1. see table 1 for description of bus operations. 2. all values are in hexadecimal. 3. shaded cells indicate read cycles. all others are write cycles. 4. during unlock and command cycles, when lower address bits are 555 or aaa as shown in table, address bits above a11 are don?t care. 5. unless otherwise noted, address bits a21?a11 are don?t cares. 6. no unlock or command cycles required when device is in read mode. 7. reset command is required to return to read mode (or to erase- suspend-read mode if previously in erase suspend) when device is in autoselect mode, or if dq5 goes high while device is providing status information. 8. fourth cycle of autoselect command sequence is a read cycle. data bits dq15?dq8 are don?t care. see autoselect command sequence section or more information. 9. device id must be read in three cycles. 10. if wp# protects highest address sector, data is 98h for factory locked and 18h for not factory locked. if wp# protects lowest address sector, data is 88h for factory locked and 08h for not factor locked. 11. data is 00h for an unprotected sector group and 01h for a protected sector group. 12. total number of cycles in command sequence is determined by number of words written to write buffer. maximum number of cycles in command sequence is 21. 13. command sequence resets device for next command after aborted write-to-buffer operation. 14. unlock bypass command is required prior to unlock bypass program command. 15. unlock bypass reset command is required to return to read mode when device is in unlock bypass mode. 16. system may read and program in non-erasing sectors, or enter autoselect mode, when in erase suspend mode. erase suspend command is valid only during a sector erase operation. 17. erase resume command is valid only during erase suspend mode. 18. command is valid when device is ready to read array data or when device is in autoselect mode.
august 14, 2003 26191f0 am29lv640mh/l 41 advance information write operation status the device provides several bits to determine the status of a program or erase operation: dq2, dq3, dq5, dq6, and dq7. ta b l e 1 2 and the following subsec- tions describe the function of these bits. dq7 and dq6 each offer a method for determining whether a program or erase operation is complete or in progress. the device also provides a hardware-based output signal, ry/by#, to determine whether an embedded program or erase operation is in progress or has been completed. dq7: data# polling the data# polling bit, dq7, indicates to the host system whether an embedded program or erase algorithm is in progress or completed, or whether the device is in erase suspend. data# polling is valid after the rising edge of the final we# pulse in the command sequence. during the embedded program algorithm, the device outputs on dq7 the com- plement of the datum programmed to dq7. this dq7 status also applies to programming during erase suspend. when the embedded program algorithm is complete, the device outputs the datum programmed to dq7. the system must provide the program address to read valid status information on dq7. if a pro- gram address falls within a protected sector, data# polling on dq7 is active for approximately 1 s, then the device returns to the read mode. during the embedded erase algorithm, data# polling produces a ?0? on dq7. when the embedded erase algorithm is co mplete, or if the device enters the erase suspend mode, data# polling produces a ?1? on dq7. the system must provide an address within any of the sectors selected for erasure to read valid status information on dq7. after an erase command sequence is written, if all sectors selected for erasing are protected, data# polling on dq7 is active for approximately 100 s, then the device returns to the read mode. if not all selected sectors are protected, the em- bedded erase algorithm erases the unprotected sectors, and ignores the selected sectors that are protected. however, if th e system reads dq7 at an address within a protected sector, the status may not be valid. just prior to the completion of an embedded program or erase operation, dq7 may change asynchronously with dq0?dq6 while output enable (oe#) is as- serted low. that is, the device may chan ge from providing status information to valid data on dq7. depending on when the system samples the dq7 output, it may read the status or valid data. even if the device has completed the program or erase operation and dq7 has valid data, the data outputs on dq0?dq6 may be still invalid. valid data on dq0?dq7 will appear on successive read cycles. ta b l e 1 2 shows the outputs for data# polling on dq7. figure 8 shows the data# polling algorithm. figure 20 in the ac characteristics section shows the data# polling timing diagram.
42 am29lv640mh/l 26191f0 august 14, 2003 advance information notes: 1. va = valid address for programming. duri ng a sector erase operation, a valid address is any sector address within the sector being erased. during chip erase, a valid address is any non-protected sector address. 2. dq7 should be rechecked even if dq5 = ?1? because dq7 may change simulta- neously with dq5. figure 8. data# polling algorithm dq7 = data? yes no no dq5 = 1? no yes yes fail pass read dq7?dq0 addr = va read dq7?dq0 addr = va dq7 = data? start
august 14, 2003 26191f0 am29lv640mh/l 43 advance information ry / b y # : r e a d y / b u sy # the ry/by# is a dedicated, open-drain output pin which indicates whether an embedded algorithm is in progress or complete. the ry/by# status is valid after the rising edge of the final we# pulse in the command sequence. since ry/by# is an open-drain output, several ry/by# pins can be tied together in parallel with a pull-up resistor to v cc . if the output is low (busy), the device is actively erasing or programming. (this includes programming in the erase suspend mode.) if the output is high (ready), the device is in the read mode, the stan dby mode, or in the erase-suspend-read mode. ta b l e 1 2 shows the outputs for ry/by#. dq6: toggle bit i toggle bit i on dq6 indicates whether an embedded program or erase algorithm is in progress or complete, or whether the device has entered the erase suspend mode. toggle bit i may be read at any address, and is valid after the rising edge of the final we# pulse in the command sequence (prior to the program or erase operation), and during the sector erase time-out. during an embedded program or erase algorithm operation, successive read cy- cles to any address cause dq6 to toggle. the system may use either oe# or ce# to control the read cycles. when the op eration is complete, dq6 stops toggling. after an erase command sequence is written, if all sectors selected for erasing are protected, dq6 toggles for approximately 100 s, then returns to reading array data. if not all selected sectors are protected, the embedded erase algo- rithm erases the unprotected sectors, and ignores the selected sectors that are protected. the system can use dq6 and dq2 together to determine whether a sector is ac- tively erasing or is erase-suspended. when the device is actively erasing (that is, the embedded erase algorithm is in progress), dq6 toggles. when the device en- ters the erase suspend mode, dq6 stops toggling. however, the system must also use dq2 to determine which sectors are erasing or erase-suspended. alter- natively, the system can use dq7 (see the subsection on dq7: data# polling ). if a program address falls within a pr otected sector, dq6 toggles for approxi- mately 1 s after the program command sequence is written, then returns to reading array data. dq6 also toggles during the erase-suspend-program mode, and stops toggling once the embedded program algorithm is complete. ta b l e 1 2 shows the outputs for toggle bit i on dq6. figure 9 shows the toggle bit algorithm. figure 21 in the ?ac characteristics? section shows the toggle bit tim- ing diagrams. figure 22 shows the differences between dq2 and dq6 in graphical form. see also the subsection on dq2: toggle bit ii .
44 am29lv640mh/l 26191f0 august 14, 2003 advance information note: the system should recheck the toggle bit even if dq5 = ?1? because the toggle bit may stop toggling as dq5 changes to ?1.? see the subsections on dq6 and dq2 for more information. figure 9. toggle bit algorithm dq2: toggle bit ii the ?toggle bit ii? on dq2, when used with dq6, indicates whether a particular sector is actively erasing (that is, the embedded erase algorithm is in progress), or whether that sector is erase-suspended. toggle bit ii is valid after the rising edge of the final we# pulse in the command sequence. dq2 toggles when the system reads at addresses within those sectors that have been selected for erasure. (the system may use either oe# or ce# to control the read cycles.) but dq2 cannot distinguish whether the sector is actively erasing or is erase-suspended. dq6, by comparison, indicates whether the device is actively start no yes yes dq5 = 1? no yes toggle bit = toggle? no program/erase operation not complete, write reset command program/erase operation complete read dq7?dq0 toggle bit = toggle? read dq7?dq0 twice read dq7?dq0
august 14, 2003 26191f0 am29lv640mh/l 45 advance information erasing, or is in erase suspend, but cannot distinguish which sectors are selected for erasure. thus, both status bits are re quired for sector and mode information. refer to ta b l e 1 2 to compare outputs for dq2 and dq6. figure 9 shows the toggle bit algorithm in flowchart form, and the section ?dq2: toggle bit ii? explains the algorithm. see also the ry/by#: ready/busy# subsec- tion. figure 21 shows the toggle bit timing diagram. figure 22 shows the differences between dq2 and dq6 in graphical form. reading toggle bits dq6/dq2 refer to figure 9 for the following discussion. whenever the system initially be- gins reading toggle bit status, it must read dq7?dq0 at least twice in a row to determine whether a toggle bit is toggling. typically, the system would note and store the value of the toggle bit after the first read. after the second read, the system would compare the new value of the toggle bit with the first. if the toggle bit is not toggling, the device has comple ted the program or erase operation. the system can read array data on dq7?dq0 on the following read cycle. however, if after the initial two read cycles, the system determines that the toggle bit is still toggling, the system also should note whether the value of dq5 is high (see the section on dq5). if it is, the system should then determine again whether the toggle bit is toggling, since the toggle bit may have stopped toggling just as dq5 went high. if the toggle bit is no longer toggling, the device has suc- cessfully completed the program or erase operation. if it is still toggling, the device did not completed the operation successfully, and the system must write the reset command to return to reading array data. the remaining scenario is that the system in itially determines that the toggle bit is toggling and dq5 has not gone high. the system may continue to monitor the toggle bit and dq5 through successive read cycles, determining the status as de- scribed in the previous paragraph. alternatively, it may choose to perform other system tasks. in this case, the system must start at the beginning of the algo- rithm when it returns to determine the status of the operation (top of figure 9). dq5: exceeded timing limits dq5 indicates whether the program, erase, or write-to-buffer time has ex- ceeded a specified internal pulse count limit. under these conditions dq5 produces a ?1,? indicating that the program or erase cycle was not successfully completed. the device may output a ?1? on dq5 if the system tries to program a ?1? to a location that was previously programmed to ?0.? only an erase operation can change a ?0? back to a ?1.? under this condition, the device halts the opera- tion, and when the timing limit has been exceeded, dq5 produces a ?1.? in all these cases, the system must writ e the reset command to return the device to the reading the array (or to erase-suspend-read if the device was previously in the erase-suspend-program mode). dq3: sector erase timer after writing a sector erase command sequence, the system may read dq3 to de- termine whether or not erasure has beg un. (the sector erase timer does not apply to the chip erase command.) if additional sectors are selected for erasure, the entire time-out also applies after each additional sector erase command. when the time-out period is complete, dq3 switches from a ?0? to a ?1.? if the time between additional sector erase commands from the system can be as-
46 am29lv640mh/l 26191f0 august 14, 2003 advance information sumed to be less than 50 s, the system need not monitor dq3. see also the sector erase command sequence section. after the sector erase command is written, the system should read the status of dq7 (data# polling) or dq6 (toggle bit i) to ensure that the device has accepted the command sequence, and then read dq3. if dq3 is ?1,? the embedded erase algorithm has begun; all further comman ds (except erase suspend) are ignored until the erase operation is complete. if dq3 is ?0,? the device will accept addi- tional sector erase commands. to ensure the command has been accepted, the system software should check the status of dq3 prior to and following each sub- sequent sector erase command. if dq3 is high on the second status check, the last command might not have been accepted. ta b l e 1 2 shows the status of dq3 relative to the other status bits. dq1: write-to-buffer abort dq1 indicates whether a write-to-buffer operation was aborted. under these conditions dq1 produces a ?1?. the system must issue the write-to-buffer-abort- reset command sequence to return the device to reading array data. see write buffer programming section for more details. table 10. write operation status notes: 1. dq5 switches to ?1? when an embedded program, embedde d erase, or write-to-buffer operation has exceeded the maximum timing limits. refer to the section on dq5 for more information. 2. dq7 and dq2 require a valid address when reading status information. refer to the appropriate subsection for further details. 3. the data# polling algorithm should be used to moni tor the last loaded write-buffer address location. 4. dq1 switches to ?1? when the device has aborted the write-to-buffer operation. status dq7 (note 2) dq6 dq5 (note 1) dq3 dq2 (note 2) dq1 ry/ by# standard mode embedded program algorithm dq7# toggle 0 n/a no toggle 0 0 embedded erase algorithm 0 toggle 0 1 toggle n/a 0 program suspend mode program- suspend read program-suspended sector invalid (not allowed) 1 non-program suspended sector data 1 erase suspend mode erase- suspend read erase-suspended sector 1 no toggle 0 n/a toggle n/a 1 non-erase suspended sector data 1 erase-suspend-program (embedded program) dq7# toggle 0 n/a n/a n/a 0 write-to- buffer busy (note 3) dq7# toggle 0 n/a n/a 0 0 abort (note 4) dq7# toggle 0 n/a n/a 1 0
august 14, 2003 26191f0 am29lv640mh/l 47 advance information absolute maximum ratings storage temperature, plastic packages . . . . . . . . . . . . . . . . .?65 c to +150 c ambient temperature with power applied . . . . . . . . . . . . . . .?65 c to +125 c voltage with respect to ground v cc (note 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .?0.5 v to +4.0 v v io . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ?0.5 v to +4.0 v a9 , oe#, acc, and reset# (note 2) . . . . . . . . . . . . ?0.5 v to +12.5 v all other pins (note 1) . . . . . . . . . . . . . . . . . . . . .?0.5 v to v cc +0.5 v output short circuit current (note 3). . . . . . . . . . . . . . . . . . . . . . . . 200 ma notes: 1. minimum dc voltage on input or i/o pins is ?0.5 v. during voltage transitions, input or i/o pins may overshoot v ss to ?2.0 v for periods of up to 20 ns. maximum dc voltage on input or i/o pins is v cc +0.5 v. see figure 10. during voltage transitions, input or i/o pins may overshoot to v cc +2.0 v for periods up to 20 ns. see figure 11. 2. minimum dc input voltage on pins a9, oe#, acc, and reset# is ?0.5 v. during voltage transitions, a9, oe#, acc, and reset# may overshoot v ss to ?2.0 v for periods of up to 20 ns. see figure 10. maximum dc input voltage on pin a9, oe#, acc, and reset# is +12.5 v which may overshoot to +14.0 v for periods up to 20 ns. 3. no more than one output may be shorted to ground at a time. duration of the short circuit should not be greater than one second. stresses above those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this data sheet is not implied. exposure of the device to absolute maximum rating con- ditions for extended periods may affect device reliability. operating ranges industrial (i) devices ambient temperature (t a )?40c to +85c supply voltages v cc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7?3.6 v v io (note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.65?3.6 v notes: 1. operating ranges define those limits between which the functionality of the device is guaranteed. 2. see ordering information section for valid v cc /v io range combinations. the i/os will not operate at 3 v when v io = 1.8 v. figure 10. maximum negative overshoot waveform figure 11. maximum positive overshoot waveform 20 ns 20 ns +0.8 v ?0.5 v 20 ns ?2.0 v 20 ns 20 ns v cc +2.0 v v cc +0.5 v 20 ns 2.0 v
48 am29lv640mh/l 26191f0 august 14, 2003 advance information dc characteristics cmos compatible notes: 1. on the wp#/acc pin only, the maximum input load current when wp# = v il is 5.0 a. 2. the i cc current listed is typically less than 2 ma/mhz, with oe# at v ih . 3. maximum i cc specifications are tested with v cc = v cc max. 4. i cc active while embedded erase or embedded program is in progress. 5. automatic sleep mode enables the low power mode when addresses remain stable for t acc + 30 ns. 6. if v io < v cc , maximum v il for ce# and dq i/os is 0.3 v io . if v io < v cc , minimum v ih for ce# and dq i/os is 0.7 v io . maximum v ih for these connections is v io + 0.3 v. 7. v cc voltage requirements. 8. v io voltage requirements. 9. includes ry/by# 10. not 100% tested. parameter symbol parameter description (notes) test conditions min typ max unit i li input load current (1) v in = v ss to v cc , v cc = v cc max 1.0 a i lit a9, acc input load current v cc = v cc max ; a9 = 12.5 v 35 a i lr reset leakage current v cc = v cc max ; reset# = 12.5 v 35 a i lo output leakage current v out = v ss to v cc , v cc = v cc max 1.0 a i cc1 v cc active read current (2, 3) ce# = v il, oe# = v ih , 5 mhz 15 20 ma 1 mhz 15 20 i cc2 v cc initial page read current (2, 3) ce# = v il, oe# = v ih 30 50 ma i cc3 v cc intra-page read current (2, 3) ce# = v il, oe# = v ih 10 20 ma i cc4 v cc active write current (3, 4) ce# = v il, oe# = v ih 50 60 ma i cc5 v cc standby current (3) ce#, reset# = v cc 0.3 v, wp# = v ih 15a i cc6 v cc reset current (3) reset# = v ss 0.3 v, wp# = v ih 15a i cc7 automatic sleep mode (3, 5) v ih = v cc 0.3 v; v il = v ss 0.3 v, wp# = v ih 15a v il1 input low voltage 1(6, 7) ?0.5 0.8 v v ih1 input high voltage 1 (6, 7) 1.9 v cc + 0.5 v v il2 input low voltage 2 (6, 8) ?0.5 0.3 x v io v v ih2 input high voltage 2 (6, 8) 1.9 v io + 0.5 v v hh voltage for acc program acceleration v cc = 2.7 ?3.6 v 11.5 12.5 v v id voltage for autoselect and temporary sector unprotect v cc = 2.7 ?3.6 v 11.5 12.5 v v ol output low voltage (9) i ol = 4.0 ma, v cc = v cc min = v io 0.15 x v io v v oh1 output high voltage i oh = ?2.0 ma, v cc = v cc min = v io 0.85 v io v v oh2 i oh = ?100 a, v cc = v cc min = v io v io ?0.4 v v lko low v cc lock-out voltage (10) 2.3 2.5 v
august 14, 2003 26191f0 am29lv640mh/l 49 advance information test conditions key to switching waveforms note: if v io < v cc , the input measurement reference level is 0.5 v io . figure 13. input waveforms and measurement levels note: diodes are in3064 or equivalent figure 12. test setup table 11. test specifications note: if v io < v cc , the reference level is 0.5 v io . 2.7 k ? c l 6.2 k ? 3.3 v device under te s t test condition all speeds unit output load 1 ttl gate output load capacitance, c l (including jig capacitance) 30 pf input rise and fall times 5 ns input pulse levels 0.0?3.0 v input timing measurement reference levels (see note) 1.5 v output timing measurement reference levels 0.5 v io v waveform inputs outputs steady changing from h to l changing from l to h don?t care, any change permitted changing, state unknown does not apply center line is high impedance state (high z) 3.0 v 0.0 v 1.5 v 0.5 v io v output measurement level input
50 am29lv640mh/l 26191f0 august 14, 2003 advance information ac characteristics read-only operations notes: 1. not 100% tested. 2. see figure 12 and table 13 for test specifications. 3. ac specifications listed are tested with v io = v cc . contact amd for information on ac operation with v io v cc . figure 14. read operation timings parameter description test setup speed options jedec std. 90r 101, 101r 112r 112 120r 120 unit t avav t rc read cycle time (note 1) min 90 100 110 120 ns t avqv t acc address to output delay ce#, oe# = v il max 90 100 110 120 ns t elqv t ce chip enable to output delay oe# = v il max 90 100 110 120 ns t pacc page access time max253030403040ns t glqv t oe output enable to output delay max 25 30 30 40 30 40 ns t ehqz t df chip enable to output high z (note 1) max 16 ns t ghqz t df output enable to output high z (note 1) max 16 ns t axqx t oh output hold time from addresses, ce# or oe#, whichever occurs first min 0 ns t oeh output enable hold time (note 1) read min 0 ns toggle and data# polling min 10 ns t oh t ce outputs we# addresses ce# oe# high z output valid high z addresses stable t rc t acc t oeh t rh t oe t rh 0 v ry/by# reset# t df
august 14, 2003 26191f0 am29lv640mh/l 51 advance information ac characteristics * figure shows device in word mode. addresses are a1?a-1 for byte mode. figure 15. page read timings a21-a2 ce# oe# a1-a0 data bus same page aa ab ac ad qa qb qc qd t acc t pacc t pacc t pacc
52 am29lv640mh/l 26191f0 august 14, 2003 advance information ac characteristics hardware reset (reset#) notes: 1. not 100% tested. 2. ac specifications listed are tested with v io = v cc . contact amd for information on ac operation with v io v cc . figure 16. reset timings parameter description all speed options unit jedec std. t ready reset# pin low (during embedded algorithms) to read mode (see note) max 20 s t ready reset# pin low (not during embedded algorithms) to read mode (see note) max 500 ns t rp reset# pulse width min 500 ns t rh reset high time before read (see note) min 50 ns t rpd reset# input low to standby mode min 20 s t rb ry/by# output high to ce#, oe# pin low min 0 ns reset# ry/by# ry/by# t rp t ready reset timings not during embedded algorithms t ready ce#, oe# t rh ce#, oe# reset timings during embedded algorithms reset# t rp t rb
august 14, 2003 26191f0 am29lv640mh/l 53 advance information ac characteristics erase and program operations notes: 1. not 100% tested. 2. see the ?erase and programming performance? section for more information. 3. for 1?16 words/1?32 bytes programmed. 4. effective write buffer specification is based upon a 16-word/32-byte write buffer operation. 5. word/byte programming specification is based upon a single word/byte programming operation not utilizing the write buffer. 6. ac specifications listed are tested with v io = v cc . contact amd for information on ac operation with v io v cc . parameter speed options jedec std. description 90r 101, 101r 112, 112r 120, 120r unit t avav t wc write cycle time (note 1) min 90 100 110 120 ns t avwl t as address setup time min 0 ns t aso address setup time to oe# low during toggle bit polling min 15 ns t wlax t ah address hold time min 45 ns t aht address hold time from ce# or oe# high during toggle bit polling min 0 ns t dvwh t ds data setup time min 45 ns t whdx t dh data hold time min 0 ns t oeph output enable high during toggle bit polling min 20 ns t ghwl t ghwl read recovery time before write (oe# high to we# low) min 0 ns t elwl t cs ce# setup time min 0 ns t wheh t ch ce# hold time min 0 ns t wlwh t wp write pulse width min 35 ns t whdl t wph write pulse width high min 30 ns t whwh1 t whwh1 write buffer program operation (notes 2, 3) typ 352 s effective write buffer program operation (notes 2, 4) per byte typ 11 s per word typ 22 s accelerated effective write buffer program operation (notes 2, 4) per byte typ 8.8 s per word typ 17.6 s single word/byte program operation (note 2, 5) byte typ 100 s word 100 single word/byte accelerated programming operation (note 2, 5) byte typ 90 word 90 s t whwh2 t whwh2 sector erase operation (note 2) typ 0.5 sec t vhh v hh rise and fall time (note 1) min 250 ns t vcs v cc setup time (note 1) min 50 s t busy we# high to ry/by# low min 90 100 110 120 ns
54 am29lv640mh/l 26191f0 august 14, 2003 advance information ac characteristics notes: 1. pa = program address, pd = program data, d out is the true data at the program address. illustration shows device in word mode. figure 17. program operation timings figure 18. accelerated program timing diagram oe# we# ce# v cc data addresses t ds t ah t dh t wp pd t whwh1 t wc t as t wph t vcs 555h pa pa read status data (last two cycles) a0h t cs statu d out program command sequence (last two cycles) t ch pa t busy ry/by# acc t vhh v hh v il or v ih v il or v ih t vhh
august 14, 2003 26191f0 am29lv640mh/l 55 advance information ac characteristics notes: 1. sa = sector address (for sector erase), va = valid addr ess for reading status data (see ?write operation status?. 2. illustration shows device in word mode. figure 19. chip/sector erase operation timings oe# ce# addresses v cc we# data 2aah sa t ah t wp t wc t as t wph 555h for chip erase 10 for chip erase 30h t ds t vcs t cs t dh 55h t ch in progress complete t whwh2 va va erase command sequence (last two cycles) read status data ry/by# t rb t busy
56 am29lv640mh/l 26191f0 august 14, 2003 advance information ac characteristics note: va = valid address. illustration shows first status cycle after command sequence, last status read cycle, and array data read cycle. figure 20. data# polling timings (during embedded algorithms) we# ce# oe# high z t oe high z dq7 dq0?dq6 ry/by# t busy complement true addresses va t oeh t ce t ch t oh t df va va status data complement status data true valid data valid data t acc t rc
august 14, 2003 26191f0 am29lv640mh/l 57 advance information ac characteristics note: va = valid address; not required for dq6. illustration shows first two status cycle after command sequence, last status read cycle, and array data read cycle. figure 21. toggle bit timings (during embedded algorithms) note: dq2 toggles only when read at an address within an erase-suspended sector. the system may use oe# or ce# to toggle dq2 and dq6. figure 22. dq2 vs. dq6 oe# ce# we# addresses t oeh t dh t aht t aso t oeph t oe valid data (first read) (second read) (stops toggling) t ceph t aht t as dq6/dq2 valid data valid status valid status valid status ry/by# enter erase erase erase enter erase suspend program erase suspend read erase suspend read erase we# dq6 dq2 erase complete erase suspend suspend program resume embedded erasing
58 am29lv640mh/l 26191f0 august 14, 2003 advance information ac characteristics temporary sector unprotect notes: 1. not 100% tested. 2. ac specifications listed are tested with v io = v cc . contact amd for information on ac operation with v io v cc . figure 23. temporary sector group unprotect timing diagram parameter all speed options jedec std description unit t vidr v id rise and fall time (see note) min 500 ns t rsp reset# setup time for temporary sector unprotect min 4 s reset# t vidr v id v ss , v il , or v ih v id v ss , v il , or v ih ce# we# ry/by# t vidr t rsp program or erase command sequence t rrb
august 14, 2003 26191f0 am29lv640mh/l 59 advance information ac characteristics note: for sector group protect, a6:a0 = 0xx0010. for sector group unprotect, a6:a0 = 1xx0010.n figure 24. sector group protect and unprotect timing diagram sector group protect: 150 s, sector group unprot ect: 15 ms 1 s reset# sa, a6, a3, a2, a1, a0 data ce# we# oe# 60h 60h 40h valid* valid* valid* status sector group protect or unprotect verify v id v ih
60 am29lv640mh/l 26191f0 august 14, 2003 advance information ac characteristics alternate ce# controlled erase and program operations notes: 1. not 100% tested. 2. see the ?erase and programming performance? section for more information. 3. for 1?16 words/1?32 bytes programmed. 4. effective write buffer specification is based upon a 16-word/32-byte write buffer operation. 5. word/byte programming specification is based upon a single word/byte programming operation not utilizing the write buffer. 6. ac specifications listed are tested with v io = v cc . contact amd for information on ac operation with v io v cc . parameter speed options jedec std. description 90r 101, 101r 112, 112r 120, 120r unit t avav t wc write cycle time (note 1) min 90 100 110 120 ns t avwl t as address setup time min 0 ns t elax t ah address hold time min 45 ns t dveh t ds data setup time min 45 ns t ehdx t dh data hold time min 0 ns t ghel t ghel read recovery time before write (oe# high to we# low) min 0 ns t wlel t ws we# setup time min 0 ns t ehwh t wh we# hold time min 0 ns t eleh t cp ce# pulse width min 45 ns t ehel t cph ce# pulse width high min 30 ns t whwh1 t whwh1 write buffer program operation (notes 2, 3) typ 352 s effective write buffer program operation (notes 2, 4) per byte typ 11 s per word typ 22 s accelerated effective write buffer program operation (notes 2, 4) per byte typ 8.8 s per word typ 17.6 s single word/byte program operation (note 2, 5) byte typ 100 s word 100 single word/byte accelerated programming operation (note 2, 5) byte typ 90 word 90 s t whwh2 t whwh2 sector erase operation (note 2) typ 0.5 sec t rh reset# high time before write min 50 ns
august 14, 2003 26191f0 am29lv640mh/l 61 advance information ac characteristics notes: 1. figure indicates last two bus cycles of a program or erase operation. 2. pa = program address, sa = sector address, pd = program data. 3. dq7# is the complement of the data written to the device. d out is the data written to the device. 4. illustration shows device in word mode. figure 25. alternate ce# controlled write (erase/program) operation timings t ghel t ws oe# ce# we# reset# t ds data t ah addresses t dh t cp dq7# d out t wc t as t cph pa data# polling a0 for program 55 for erase t rh t whwh1 or 2 ry/by# t wh pd for program 30 for sector erase 10 for chip erase 555 for program 2aa for erase pa for program sa for sector erase 555 for chip erase t busy
62 am29lv640mh/l 26191f0 august 14, 2003 advance information erase and programming performance notes: 1. typical program and erase times as sume the following conditions: 25 c, 3.0 v v cc . programming specifications assume that all bits are programmed to 00h. 2. maximum values are measured at v cc = 3.0 v, worst case temperature. maximum values are valid up to and including 100,000 program/erase cycles. 3. word/byte programming specification is based upon a single word/byte programming operation not utilizing the write buffer. 4. for 1-16 words or 1-32 bytes programmed ina single write buffer programming operation. 5. effective write buffer specification is calculated on a per-word/per-byte basis for a 16-word/32-byte write buffer operation. 6. in the pre-programming step of the embedded erase algorithm, all bits are programmed to 00h before erasure. 7. system-level overhead is the time required to execute the command sequence(s) for the program command. see tables 12 and 11 for further information on command definitions. 8. the device has a minimum erase and program cycle endurance of 100,000 cycles. latchup characteristics note: includes all pins except v cc . test conditions: v cc = 3.0 v, one pin at a time. parameter typ (note 1) max (note 2) unit comments sector erase time 0.5 15 sec chip erase time 32 128 sec single word/byte program time (note 3) byte 100 tbd s word 100 tbd s accelerated single word/byte program time (note 3) byte 90 tbd s word 90 tbd s total write buffer program time (note 4) 352 tbd s effective write buffer program time (note 5) per byte 11 tbd s per word 22 tbd s total accelerated effective write buffer program time (note 4) 282 tbd s effective accelerated write buffer program time (note 4) byte 8.8 tbd s word 17.6 tbd s chip program time 92 tbd sec description min max input voltage with respect to v ss on all pins except i/o pins (including a9, oe#, and reset#) ?1.0 v 12.5 v input voltage with respect to v ss on all i/o pins ?1.0 v v cc + 1.0 v v cc current ?100 ma +100 ma
august 14, 2003 26191f0 am29lv640mh/l 63 advance information tsop pin and bga package capacitance notes: 1. sampled, not 100% tested. 2. test conditions t a = 25c, f = 1.0 mhz. data retention parameter symbol parameter description test setup typ max unit c in input capacitance v in = 0 tsop 6 7.5 pf fine-pitch bga 4.2 5.0 pf c out output capacitance v out = 0 tsop 8.5 12 pf fine-pitch bga 5.4 6.5 pf c in2 control pin capacitance v in = 0 tsop 7.5 9 pf fine-pitch bga 3.9 4.7 pf parameter description test conditions min unit minimum pattern data retention time 150 c10years 125 c20years
64 am29lv640mh/l 26191f0 august 14, 2003 advance information physical dimensions ts056/tsr056?56-pin standard and reverse pinout thin small outline package (tsop) notes: 1 controlling dimensions are in millimeters (mm). (dimensioning and tolerancing conforms to ansi y14.5m-1982.) 2 pin 1 identifier for standard pin out (die up). 3 pin 1 identifier for reverse pin out (die down), ink or laser mark. 4 to be determined at the seating plane -c- . the seating plane is defined as the plane of contact that is made when the package leads are allowed to rest freely on a flat horizontal surface. 5 dimensions d1 and e do not include mold protrusion. allowable mold protusion is 0.15 mm per side. 6 dimension b does not include dambar protusion. allowable dambar protusion shall be 0.08 mm total in excess of b dimension at max material condition. minimum space between protrusion and an adjacent lead to be 0.07 mm. 7 these dimesions apply to the flat section of the lead between 0.10 mm and 0.25 mm from the lead tip. 8. lead coplanarity shall be within 0.10 mm as measured from the seating plane. 9 dimension "e" is measured at the centerline of the leads. 3160\38.10a mo-142 (b) ec ts/tsr 56 nom. --- --- 1.00 1.20 0.15 1.05 max. --- min. 0.95 0.20 0.23 0.17 0.22 0.27 0.17 --- 0.16 0.10 --- 0.21 0.10 20.00 20.20 19.90 14.00 14.10 13.90 0.60 0.70 0.50 3? 5? 0? --- 0.20 0.08 56 18.40 18.50 18.30 0.05 0.50 basic e r b1 jedec package symbol a a2 a1 d1 d c1 c b e l n o
august 14, 2003 26191f0 am29lv640mh/l 65 advance information physical dimensions laa064?64-ball fortified ball grid array ( f bga) 13 x 11 mm package
66 am29lv640mh/l 26191f0 august 14, 2003 advance information revision summary revision a (march 19, 2002) initial release as abbreviated advance information data sheet. this document contains information that was previously released in publication number 25301. ordering information the package marking for the fortified bga option has been updated. physical dimensions added drawing that shows both ts056 and tsr056 specifications. revision b (april 26, 2002) expanded data sheet to full specification version. revision c (may 23, 2002) changed packaging from 63-ball fbga to 64-ball fortified bga. changed block diagram: moved v io from ry/by# to input/output buffers. changed note about wp#/acc pin to indicate internal pullup to v cc . modified table 4: sector group protection/unprotection address table. changed 47h address data from 0004h to 0001h in table 9. revision d (august 8, 2002) alternate ce# controlled erase and program operations added t rh parameter to table. erase and program operations added t busy parameter to table. tsop and bga pin capacitance added the fbga package. program suspend/program resume command sequence changed 15 s typical to maximum and added 5 s typical. erase suspend/erase resume commands changed typical from 20 s to 5 s and added a maximum of 20 s. special package handling instructions modified the special handling wording. dc characteristics table deleted the iacc specification row. cfi changed text in the third paragraph of cfi to read ?reading array data.? revision d+1 (september 10, 2002) product selector guide added note 2. ordering information added note 1. sector erase command sequence deleted statement that describes the outcome of when the embedded erase op- eration is in progress.
august 14, 2003 26191f0 am29lv640mh/l 67 advance information revision e (december 5, 2002) product selector guide and read-only characteristics added a 30 ns option to t pacc and t oe standard for the 112r and 120r speed options. customer lockable: secsi sector not programmed or protected at the factory. added second bullet, secsi sector-protect verify text and figure 3. secsi sector flash memory region, and enter secsi sector/exit secsi sector command sequence noted that the acc function and unlock bypass modes are not available when the secsi sector is enabled. byte/word program command sequence, sector erase command sequence, and chip erase command sequence noted that the secsi sector, autoselect, and cfi functions are unavailable when a program or erase operation is in progress. common flash memory interface (cfi) changed cfi website address figure 6. program suspend/program resume change wait time to 15 s. cmos compatible added i lr row to table. changed v ih1 and v ih2 minimum to 1.9. removed typos in notes. hardware reset, cmos tables, erase and program operations, temporary sector unprotect, and alternate ce# controlled erase and program operations added note. revision e+1 (february 16, 2003) distinctive characteristics corrected performance characteristics. product selector guide added note 2. ordering information corrected valid combinations table. added note. ac characteristics removed 90, 90r speed option. added note input values in the t whwh 1 and t whwh 2 parameters in the erase and program op- tions table that were previously tbd. also, added note 5. input values in the t whwh 1 and t whwh 2 parameters in the alternate ce# con- trolled erase and program options table that were previously tbd. also, added note 5. erase and programming performance input values into table that were previously tbd. added notes 3 and 4.
68 am29lv640mh/l 26191f0 august 14, 2003 advance information revision e+2 (june 11, 2003) ordering information added 90r speed grade, modified note. erase and programming performance modified table, supplied values for typical. revision f (august 14, 2003) global converted document to new spansion template. ordering information added note for ordering and marking information related to ?n? (factory-pro- tected secsi sector) devices. command definitions corrected program erase/suspend addressing from ba to don?t care. dc characteristics table corrected note reference number on v ol specification. hardware reset (reset#) added t rb specification to table. trademarks and notice this document contains fasl confidential information. the contents of this document may not be copied nor duplicated in any for m, in whole or in part, without prior written consent from fasl. the information in this document is subject to change without notice. product and comp any names are trademarks or registered trademarks of their respective owners copyright 2003 fasl llc. all rights reserved.

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